Merge 3b6dc3d456061258f7b8067609980b3bcfe9b908 on remote branch (5ae83f94) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/cam_cdm/cam_cdm_hw_core.c

+36 −6

Original line number	Diff line number	Diff line
		@@ -543,7 +543,7 @@ int cam_hw_cdm_wait_for_bl_fifo(
		CAM_DBG(CAM_CDM,
		"BL slot available_cnt=%d requested=%d",
		(available_bl_slots - 1), bl_count);
		rc = bl_count;
		rc = available_bl_slots - 1;
		break;
		} else if (0 == (available_bl_slots - 1)) {
		rc = cam_hw_cdm_enable_bl_done_irq(cdm_hw,
		@@ -569,7 +569,7 @@ int cam_hw_cdm_wait_for_bl_fifo(
		if (cam_hw_cdm_enable_bl_done_irq(cdm_hw,
		false, fifo_idx))
		CAM_ERR(CAM_CDM, "Disable BL done irq failed");
		rc = 0;
		rc = 1;
		CAM_DBG(CAM_CDM, "CDM HW is ready for data");
		} else {
		rc = (bl_count - (available_bl_slots - 1));
		@@ -898,8 +898,6 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
		rc = -EIO;
		break;
		}
		} else {
		write_count--;
		}

		if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) {
		@@ -966,6 +964,7 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
		rc = -EIO;
		break;
		}
		write_count--;
		}
		} else {
		CAM_ERR(CAM_CDM,
		@@ -1002,27 +1001,58 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
		rc = -EIO;
		break;
		}
		write_count--;
		CAM_DBG(CAM_CDM, "commit success BL %d tag=%d",
		i, core->bl_fifo[fifo_idx].bl_tag);
		}
		core->bl_fifo[fifo_idx].bl_tag++;

		if (cdm_cmd->cmd[i].enable_debug_gen_irq) {
		if (write_count == 0) {
		write_count =
		cam_hw_cdm_wait_for_bl_fifo(
		cdm_hw, 1, fifo_idx);
		if (write_count < 0) {
		CAM_ERR(CAM_CDM,
		"wait for bl fifo failed %d:%d",
		i, req->data->cmd_arrary_count);
		rc = -EIO;
		break;
		}
		}

		rc = cam_hw_cdm_submit_debug_gen_irq(cdm_hw,
		fifo_idx);
		if (rc == 0)
		if (rc == 0) {
		write_count--;
		core->bl_fifo[fifo_idx].bl_tag++;
		}
		if (core->bl_fifo[fifo_idx].bl_tag >=
		(bl_fifo->bl_depth -
		1))
		core->bl_fifo[fifo_idx].bl_tag = 0;
		}

		if ((req->data->flag == true) &&
		if ((!rc) && (req->data->flag == true) &&
		(i == (req->data->cmd_arrary_count -
		1))) {

		if (write_count == 0) {
		write_count =
		cam_hw_cdm_wait_for_bl_fifo(
		cdm_hw, 1, fifo_idx);
		if (write_count < 0) {
		CAM_ERR(CAM_CDM,
		"wait for bl fifo failed %d:%d",
		i, req->data->cmd_arrary_count);
		rc = -EIO;
		break;
		}
		}

		if (core->arbitration !=
		CAM_CDM_ARBITRATION_PRIORITY_BASED) {

		rc = cam_hw_cdm_submit_gen_irq(
		cdm_hw, req, fifo_idx,
		cdm_cmd->gen_irq_arb);

drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c

+9 −2

Original line number	Diff line number	Diff line
		@@ -43,6 +43,8 @@

		static struct cam_ope_hw_mgr *ope_hw_mgr;

		static int cam_ope_req_timer_reset(struct cam_ope_ctx *ctx_data);

		static int cam_ope_mgr_get_rsc_idx(struct cam_ope_ctx *ctx_data,
		struct ope_io_buf_info *in_io_buf)
		{
		@@ -125,6 +127,8 @@ static int cam_ope_mgr_process_cmd(void priv, void data)
		if (task_data->req_id > ctx_data->last_flush_req)
		ctx_data->last_flush_req = 0;

		cam_ope_req_timer_reset(ctx_data);

		rc = cam_cdm_submit_bls(ctx_data->ope_cdm.cdm_handle, cdm_cmd);

		if (!rc)
		@@ -1083,8 +1087,7 @@ static int cam_ope_calc_total_clk(struct cam_ope_hw_mgr *hw_mgr,
		hw_mgr_clk_info->base_clk = 0;
		for (i = 0; i < OPE_CTX_MAX; i++) {
		ctx_data = &hw_mgr->ctx[i];
		if (ctx_data->ctx_state == OPE_CTX_STATE_ACQUIRED &&
		ctx_data->ope_acquire.dev_type == dev_type)
		if (ctx_data->ctx_state == OPE_CTX_STATE_ACQUIRED)
		hw_mgr_clk_info->base_clk +=
		ctx_data->clk_info.base_clk;
		}
		@@ -3626,6 +3629,7 @@ static int cam_ope_mgr_hw_dump(void hw_priv, void hw_dump_args)
		}

		mutex_lock(&hw_mgr->hw_mgr_mutex);
		mutex_lock(&ctx_data->ctx_mutex);

		CAM_INFO(CAM_OPE, "Req %lld", dump_args->request_id);
		for (idx = 0; idx < CAM_CTX_REQ_MAX; idx++) {
		@@ -3639,6 +3643,7 @@ static int cam_ope_mgr_hw_dump(void hw_priv, void hw_dump_args)

		/* no matching request found */
		if (idx == CAM_CTX_REQ_MAX) {
		mutex_unlock(&ctx_data->ctx_mutex);
		mutex_unlock(&hw_mgr->hw_mgr_mutex);
		return 0;
		}
		@@ -3656,6 +3661,7 @@ static int cam_ope_mgr_hw_dump(void hw_priv, void hw_dump_args)
		req_ts.tv_nsec/NSEC_PER_USEC,
		cur_ts.tv_sec,
		cur_ts.tv_nsec/NSEC_PER_USEC);
		mutex_unlock(&ctx_data->ctx_mutex);
		mutex_unlock(&hw_mgr->hw_mgr_mutex);
		return 0;
		}
		@@ -3667,6 +3673,7 @@ static int cam_ope_mgr_hw_dump(void hw_priv, void hw_dump_args)
		cur_ts.tv_sec,
		cur_ts.tv_nsec/NSEC_PER_USEC);

		mutex_unlock(&ctx_data->ctx_mutex);
		mutex_unlock(&hw_mgr->hw_mgr_mutex);
		return 0;
		}

drivers/cam_req_mgr/cam_req_mgr_core.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -2930,7 +2930,7 @@ static int cam_req_mgr_cb_notify_trigger(

		task = cam_req_mgr_workq_get_task(link->workq);
		if (!task) {
		CAM_ERR(CAM_CRM, "no empty task frame %lld",
		CAM_ERR_RATE_LIMIT(CAM_CRM, "no empty task frame %lld",
		trigger_data->frame_id);
		rc = -EBUSY;
		goto end;

drivers/cam_sensor_module/cam_cci/cam_cci_core.c

+19 −14

Original line number	Diff line number	Diff line
		@@ -177,10 +177,11 @@ static int32_t cam_cci_lock_queue(struct cci_device *cci_dev,
		return cam_cci_write_i2c_queue(cci_dev, val, master, queue);
		}

		#ifdef DUMP_CCI_REGISTERS
		static void cam_cci_dump_registers(struct cci_device *cci_dev,

		void cam_cci_dump_registers(struct cci_device *cci_dev,
		enum cci_i2c_master_t master, enum cci_i2c_queue_t queue)
		{
		uint32_t dump_en = 0;
		uint32_t read_val = 0;
		uint32_t i = 0;
		uint32_t reg_offset = 0;
		@@ -188,6 +189,14 @@ static void cam_cci_dump_registers(struct cci_device *cci_dev,
		uint32_t read_data_reg_offset = 0x0;
		void __iomem *base = cci_dev->soc_info.reg_map[0].mem_base;

		dump_en = cci_dev->dump_en;
		if (!(dump_en & CAM_CCI_NACK_DUMP_EN) &&
		!(dump_en & CAM_CCI_TIMEOUT_DUMP_EN)) {
		CAM_DBG(CAM_CCI,
		"Nack and Timeout dump is not enabled");
		return;
		}

		/* CCI Top Registers */
		CAM_INFO(CAM_CCI, "**CCI TOP Registers **");
		for (i = 0; i < DEBUG_TOP_REG_COUNT; i++) {
		@@ -238,7 +247,7 @@ static void cam_cci_dump_registers(struct cci_device *cci_dev,
		reg_offset, read_val);
		}
		}
		#endif
		EXPORT_SYMBOL(cam_cci_dump_registers);

		static uint32_t cam_cci_wait(struct cci_device *cci_dev,
		enum cci_i2c_master_t master,
		@@ -256,9 +265,8 @@ static uint32_t cam_cci_wait(struct cci_device *cci_dev,
		CAM_DBG(CAM_CCI, "wait DONE_for_completion_timeout");

		if (rc <= 0) {
		#ifdef DUMP_CCI_REGISTERS
		cam_cci_dump_registers(cci_dev, master, queue);
		#endif

		CAM_ERR(CAM_CCI, "wait for queue: %d", queue);
		if (rc == 0)
		rc = -ETIMEDOUT;
		@@ -1031,9 +1039,8 @@ static int32_t cam_cci_burst_read(struct v4l2_subdev *sd,
		CAM_ERR(CAM_CCI,
		"wait_for_completion_timeout rc = %d FIFO buf_lvl:0x%x",
		rc, val);
		#ifdef DUMP_CCI_REGISTERS
		cam_cci_dump_registers(cci_dev, master, queue);
		#endif

		cam_cci_flush_queue(cci_dev, master);
		goto rel_mutex_q;
		}
		@@ -1111,10 +1118,9 @@ static int32_t cam_cci_burst_read(struct v4l2_subdev *sd,
		CAM_ERR(CAM_CCI,
		"Failed to receive RD_DONE irq rc = %d FIFO buf_lvl:0x%x",
		rc, val);
		#ifdef DUMP_CCI_REGISTERS
		cam_cci_dump_registers(cci_dev,
		master, queue);
		#endif

		cam_cci_flush_queue(cci_dev, master);
		goto rel_mutex_q;
		}
		@@ -1288,9 +1294,8 @@ static int32_t cam_cci_read(struct v4l2_subdev *sd,
		rc = wait_for_completion_timeout(
		&cci_dev->cci_master_info[master].rd_done, CCI_TIMEOUT);
		if (rc <= 0) {
		#ifdef DUMP_CCI_REGISTERS
		cam_cci_dump_registers(cci_dev, master, queue);
		#endif

		if (rc == 0)
		rc = -ETIMEDOUT;
		val = cam_io_r_mb(base +

drivers/cam_sensor_module/cam_cci/cam_cci_dev.c

+101 −4

Original line number	Diff line number	Diff line
		@@ -11,6 +11,7 @@
		#define CCI_MAX_DELAY 1000000

		static struct v4l2_subdev *g_cci_subdev[MAX_CCI];
		static struct dentry *debugfs_root;

		struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index)
		{
		@@ -223,9 +224,22 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
		}
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_ERROR_BMSK) {
		cci_dev->cci_master_info[MASTER_0].status = -EINVAL;
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_NACK_ERROR_BMSK)
		CAM_ERR(CAM_CCI, "Base:%pK, M0 NACK ERROR: 0x%x",
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERROR_BMSK) {
		CAM_ERR(CAM_CCI, "Base:%pK, M0_Q0 NACK ERROR: 0x%x",
		base, irq_status0);
		cam_cci_dump_registers(cci_dev, MASTER_0,
		QUEUE_0);
		complete_all(&cci_dev->cci_master_info[MASTER_0]
		.report_q[QUEUE_0]);
		}
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERROR_BMSK) {
		CAM_ERR(CAM_CCI, "Base:%pK, M0_Q1 NACK ERROR: 0x%x",
		base, irq_status0);
		cam_cci_dump_registers(cci_dev, MASTER_0,
		QUEUE_1);
		complete_all(&cci_dev->cci_master_info[MASTER_0]
		.report_q[QUEUE_1]);
		}
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_ERROR_BMSK)
		CAM_ERR(CAM_CCI,
		"Base:%pK, M0 QUEUE_OVER/UNDER_FLOW OR CMD ERR: 0x%x",
		@@ -238,9 +252,22 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
		}
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_ERROR_BMSK) {
		cci_dev->cci_master_info[MASTER_1].status = -EINVAL;
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_NACK_ERROR_BMSK)
		CAM_ERR(CAM_CCI, "Base:%pK, M1 NACK ERROR: 0x%x",
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERROR_BMSK) {
		CAM_ERR(CAM_CCI, "Base:%pK, M1_Q0 NACK ERROR: 0x%x",
		base, irq_status0);
		cam_cci_dump_registers(cci_dev, MASTER_1,
		QUEUE_0);
		complete_all(&cci_dev->cci_master_info[MASTER_1]
		.report_q[QUEUE_0]);
		}
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERROR_BMSK) {
		CAM_ERR(CAM_CCI, "Base:%pK, M1_Q1 NACK ERROR: 0x%x",
		base, irq_status0);
		cam_cci_dump_registers(cci_dev, MASTER_1,
		QUEUE_1);
		complete_all(&cci_dev->cci_master_info[MASTER_1]
		.report_q[QUEUE_1]);
		}
		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_ERROR_BMSK)
		CAM_ERR(CAM_CCI,
		"Base:%pK, M1 QUEUE_OVER_UNDER_FLOW OR CMD ERROR:0x%x",
		@@ -369,6 +396,70 @@ static long cam_cci_subdev_fops_compat_ioctl(struct file *file,
		}
		#endif

		static int cam_cci_get_debug(void data, u64 val)
		{
		struct cci_device cci_dev = (struct cci_device )data;

		*val = cci_dev->dump_en;

		return 0;
		}

		static int cam_cci_set_debug(void *data, u64 val)
		{
		struct cci_device cci_dev = (struct cci_device )data;

		cci_dev->dump_en = val;

		return 0;
		}

		DEFINE_DEBUGFS_ATTRIBUTE(cam_cci_debug,
		cam_cci_get_debug,
		cam_cci_set_debug, "%16llu\n");

		static int cam_cci_create_debugfs_entry(struct cci_device *cci_dev)
		{
		int rc = 0;
		struct dentry *dbgfileptr = NULL;

		if (!debugfs_root) {
		dbgfileptr = debugfs_create_dir("cam_cci", NULL);
		if (!dbgfileptr) {
		CAM_ERR(CAM_CCI, "debugfs directory creation fail");
		rc = -ENOENT;
		goto end;
		}
		debugfs_root = dbgfileptr;
		}

		if (cci_dev->soc_info.index == 0) {
		dbgfileptr = debugfs_create_file("en_dump_cci0", 0644,
		debugfs_root, cci_dev, &cam_cci_debug);
		if (IS_ERR(dbgfileptr)) {
		if (PTR_ERR(dbgfileptr) == -ENODEV)
		CAM_WARN(CAM_CCI, "DebugFS not enabled");
		else {
		rc = PTR_ERR(dbgfileptr);
		goto end;
		}
		}
		} else {
		dbgfileptr = debugfs_create_file("en_dump_cci1", 0644,
		debugfs_root, cci_dev, &cam_cci_debug);
		if (IS_ERR(dbgfileptr)) {
		if (PTR_ERR(dbgfileptr) == -ENODEV)
		CAM_WARN(CAM_CCI, "DebugFS not enabled");
		else {
		rc = PTR_ERR(dbgfileptr);
		goto end;
		}
		}
		}
		end:
		return rc;
		}

		static int cam_cci_platform_probe(struct platform_device *pdev)
		{
		struct cam_cpas_register_params cpas_parms;
		@@ -448,6 +539,11 @@ static int cam_cci_platform_probe(struct platform_device *pdev)
		cpas_parms.client_handle);
		new_cci_dev->cpas_handle = cpas_parms.client_handle;

		rc = cam_cci_create_debugfs_entry(new_cci_dev);
		if (rc) {
		CAM_WARN(CAM_CCI, "debugfs creation failed");
		rc = 0;
		}
		return rc;

		cci_unregister_subdev:
		@@ -464,6 +560,7 @@ static int cam_cci_device_remove(struct platform_device *pdev)
		v4l2_get_subdevdata(subdev);

		cam_cpas_unregister_client(cci_dev->cpas_handle);
		debugfs_remove_recursive(debugfs_root);
		cam_cci_soc_remove(pdev, cci_dev);
		devm_kfree(&pdev->dev, cci_dev);
		return 0;