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Commit 5a9f8395 authored by Manikanta Kanamarlapudi's avatar Manikanta Kanamarlapudi Committed by Gerrit - the friendly Code Review server
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msm: vidc: Update clock cycles 



Update clock cycles of vsp and vpp
required for per MB in bengal target.

CRs-Fixed: 2558188
Change-Id: Ifa39458123dfe2b687b0865e119e23aaf5613713
Signed-off-by: default avatarManikanta Kanamarlapudi <kmanikan@codeaurora.org>
parent c6eec14a

msm/vidc/msm_vidc_platform.c

+5 −5
Original line number Diff line number Diff line
@@ -103,11 +103,11 @@ static struct msm_vidc_codec_data sm6150_codec_data[] = { 
};



static struct msm_vidc_codec_data bengal_codec_data[] =  {

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 125, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 125, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 50, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 50, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 50, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 0, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 0, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 0, 440, 440),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 0, 440, 440),

	CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 0, 440, 440),

};



/* Update with 855 data */