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Commit 5a7d8a28 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "This has been sitting in -next for a while with no objections and all
  MIPS defconfigs except one are building fine; that one platform got
  broken by another patch in your tree and I'm going to submit a patch
  separately.

   - a handful of fixes that didn't make 3.11
   - a few bits of Octeon 3 support with more to come for a later
     release
   - platform enhancements for Octeon, ath79, Lantiq, Netlogic and
     Ralink SOCs
   - a GPIO driver for the Octeon
   - some dusting off of the DECstation code
   - the usual dose of cleanups"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (65 commits)
  MIPS: DMA: Fix BUG due to smp_processor_id() in preemptible code
  MIPS: kexec: Fix random crashes while loading crashkernel
  MIPS: kdump: Skip walking indirection page for crashkernels
  MIPS: DECstation HRT calibration bug fixes
  MIPS: Export copy_from_user_page() (needed by lustre)
  MIPS: Add driver for the built-in PCI controller of the RT3883 SoC
  MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000
  MIPS: ralink: Add support for reset-controller API
  MIPS: ralink: mt7620: Add cpu-feature-override header
  MIPS: ralink: mt7620: Add spi clock definition
  MIPS: ralink: mt7620: Add wdt clock definition
  MIPS: ralink: mt7620: Improve clock frequency detection
  MIPS: ralink: mt7620: This SoC has EHCI and OHCI hosts
  MIPS: ralink: mt7620: Add verbose ram info
  MIPS: ralink: Probe clocksources from OF
  MIPS: ralink: Add support for systick timer found on newer ralink SoC
  MIPS: ralink: Add support for periodic timer irq
  MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards
  MIPS: Netlogic: Add support for USB on XLP2xx
  MIPS: Netlogic: XLP2xx update for I2C controller
  ...
parents e0ea4045 eb37e6dd

Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt

0 → 100644
+190 −0
Original line number Diff line number Diff line 
* Mediatek/Ralink RT3883 PCI controller



1) Main node



   Required properties:



   - compatible: must be "ralink,rt3883-pci"



   - reg: specifies the physical base address of the controller and

     the length of the memory mapped region.



   - #address-cells: specifies the number of cells needed to encode an

     address. The value must be 1.



   - #size-cells: specifies the number of cells used to represent the size

     of an address. The value must be 1.



   - ranges: specifies the translation between child address space and parent

     address space



  Optional properties:



   - status: indicates the operational status of the device.

     Value must be either "disabled" or "okay".



2) Child nodes



   The main node must have two child nodes which describes the built-in

   interrupt controller and the PCI host bridge.



   a) Interrupt controller:



   Required properties:



   - interrupt-controller: identifies the node as an interrupt controller



   - #address-cells: specifies the number of cells needed to encode an

     address. The value must be 0. As such, 'interrupt-map' nodes do not

     have to specify a parent unit address.



   - #interrupt-cells: specifies the number of cells needed to encode an

     interrupt source. The value must be 1.



   - interrupt-parent: the phandle for the interrupt controller that

     services interrupts for this device.



   - interrupts: specifies the interrupt source of the parent interrupt

     controller. The format of the interrupt specifier depends on the

     parent interrupt controller.



   b) PCI host bridge:



   Required properties:



   - #address-cells: specifies the number of cells needed to encode an

     address. The value must be 0.



   - #size-cells: specifies the number of cells used to represent the size

     of an address. The value must be 2.



   - #interrupt-cells: specifies the number of cells needed to encode an

     interrupt source. The value must be 1.



   - device_type: must be "pci"



   - bus-range: PCI bus numbers covered



   - ranges: specifies the ranges for the PCI memory and I/O regions



   - interrupt-map-mask,

   - interrupt-map: standard PCI properties to define the mapping of the

     PCI interface to interrupt numbers.



   The PCI host bridge node migh have additional sub-nodes representing

   the onboard PCI devices/PCI slots. Each such sub-node must have the

   following mandatory properties:



     - reg: used only for interrupt mapping, so only the first four bytes

       are used to refer to the correct bus number and device number.



     - device_type: must be "pci"



   If a given sub-node represents a PCI bridge it must have following

   mandatory properties as well:



     - #address-cells: must be set to <3>



     - #size-cells: must set to <2>



     - #interrupt-cells: must be set to <1>



     - interrupt-map-mask,

     - interrupt-map: standard PCI properties to define the mapping of the

       PCI interface to interrupt numbers.



   Besides the required properties the sub-nodes may have these optional

   properties:



     - status: indicates the operational status of the sub-node.

       Value must be either "disabled" or "okay".



3) Example:



   a) SoC specific dtsi file:



	pci@10140000 {

		compatible = "ralink,rt3883-pci";

		reg = <0x10140000 0x20000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges; /* direct mapping */



		status = "disabled";



		pciintc: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;



			interrupt-parent = <&cpuintc>;

			interrupts = <4>;

		};



		host-bridge {

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;



			device_type = "pci";



			bus-range = <0 255>;

			ranges = <

				0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */

				0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */

			>;



			interrupt-map-mask = <0xf800 0 0 7>;

			interrupt-map = <

				/* IDSEL 17 */

				0x8800 0 0 1 &pciintc 18

				0x8800 0 0 2 &pciintc 18

				0x8800 0 0 3 &pciintc 18

				0x8800 0 0 4 &pciintc 18

				/* IDSEL 18 */

				0x9000 0 0 1 &pciintc 19

				0x9000 0 0 2 &pciintc 19

				0x9000 0 0 3 &pciintc 19

				0x9000 0 0 4 &pciintc 19

			>;



			pci-bridge@1 {

				reg = <0x0800 0 0 0 0>;

				device_type = "pci";

				#interrupt-cells = <1>;

				#address-cells = <3>;

				#size-cells = <2>;



				interrupt-map-mask = <0x0 0 0 0>;

				interrupt-map = <0x0 0 0 0 &pciintc 20>;



				status = "disabled";

			};



			pci-slot@17 {

				reg = <0x8800 0 0 0 0>;

				device_type = "pci";



				status = "disabled";

			};



			pci-slot@18 {

				reg = <0x9000 0 0 0 0>;

				device_type = "pci";



				status = "disabled";

			};

		};

	};



   b) Board specific dts file:



	pci@10140000 {

		status = "okay";



		host-bridge {

			pci-bridge@1 {

				status = "okay";

			};

		};

	};

arch/mips/Kconfig

+5 −14
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ config ATH79 
	select CSRC_R4K

	select DMA_NONCOHERENT

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select IRQ_CPU

	select MIPS_MACHINE

	select SYS_HAS_CPU_MIPS32_R2
@@ -131,7 +132,6 @@ config BCM63XX 
	select IRQ_CPU

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348

	select NR_CPUS_DEFAULT_2

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_HAS_EARLY_PRINTK
@@ -445,6 +445,8 @@ config RALINK 
	select SYS_HAS_EARLY_PRINTK

	select HAVE_MACH_CLKDEV

	select CLKDEV_LOOKUP

	select ARCH_HAS_RESET_CONTROLLER

	select RESET_CONTROLLER



config SGI_IP22

	bool "SGI IP22 (Indy/Indigo2)"
@@ -609,7 +611,6 @@ config SIBYTE_SWARM 
	select BOOT_ELF32

	select DMA_COHERENT

	select HAVE_PATA_PLATFORM

	select NR_CPUS_DEFAULT_2

	select SIBYTE_SB1250

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1
@@ -623,7 +624,6 @@ config SIBYTE_LITTLESUR 
	select BOOT_ELF32

	select DMA_COHERENT

	select HAVE_PATA_PLATFORM

	select NR_CPUS_DEFAULT_2

	select SIBYTE_SB1250

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1
@@ -635,7 +635,6 @@ config SIBYTE_SENTOSA 
	bool "Sibyte BCM91250E-Sentosa"

	select BOOT_ELF32

	select DMA_COHERENT

	select NR_CPUS_DEFAULT_2

	select SIBYTE_SB1250

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1
@@ -731,6 +730,7 @@ config CAVIUM_OCTEON_SOC 
	select USB_ARCH_HAS_OHCI

	select USB_ARCH_HAS_EHCI

	select HOLES_IN_ZONE

	select ARCH_REQUIRE_GPIOLIB

	help

	  This option supports all of the Octeon reference boards from Cavium

	  Networks. It builds a kernel that dynamically determines the Octeon
@@ -1860,7 +1860,6 @@ config MIPS_MT_SMP 
	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select MIPS_MT

	select NR_CPUS_DEFAULT_2

	select SMP

	select SYS_SUPPORTS_SCHED_SMT if SMP

	select SYS_SUPPORTS_SMP
@@ -2171,12 +2170,6 @@ config SYS_SUPPORTS_MIPS_CMP 
config SYS_SUPPORTS_SMP

	bool



config NR_CPUS_DEFAULT_1

	bool



config NR_CPUS_DEFAULT_2

	bool



config NR_CPUS_DEFAULT_4

	bool
@@ -2194,10 +2187,8 @@ config NR_CPUS_DEFAULT_64 


config NR_CPUS

	int "Maximum number of CPUs (2-64)"

	range 1 64 if NR_CPUS_DEFAULT_1

	range 2 64

	depends on SMP

	default "1" if NR_CPUS_DEFAULT_1

	default "2" if NR_CPUS_DEFAULT_2

	default "4" if NR_CPUS_DEFAULT_4

	default "8" if NR_CPUS_DEFAULT_8

	default "16" if NR_CPUS_DEFAULT_16

arch/mips/Makefile

+29 −5
Original line number Diff line number Diff line
@@ -194,6 +194,8 @@ include $(srctree)/arch/mips/Kbuild.platforms 
ifdef CONFIG_PHYSICAL_START

load-y					= $(CONFIG_PHYSICAL_START)

endif

entry-y				= 0x$(shell $(NM) vmlinux 2>/dev/null \

					| grep "\bkernel_entry\b" | cut -f1 -d \ )



cflags-y			+= -I$(srctree)/arch/mips/include/asm/mach-generic

drivers-$(CONFIG_PCI)		+= arch/mips/pci/
@@ -225,6 +227,9 @@ KBUILD_CFLAGS += $(cflags-y) 
KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)

KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)



bootvars-y	= VMLINUX_LOAD_ADDRESS=$(load-y) \

		  VMLINUX_ENTRY_ADDRESS=$(entry-y)



LDFLAGS			+= -m $(ld-emul)



ifdef CONFIG_CC_STACKPROTECTOR
@@ -254,9 +259,25 @@ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ 
# suspend and hibernation support

drivers-$(CONFIG_PM)	+= arch/mips/power/



# boot image targets (arch/mips/boot/)

boot-y			:= vmlinux.bin

boot-y			+= vmlinux.ecoff

boot-y			+= vmlinux.srec

ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0)

boot-y			+= uImage

boot-y			+= uImage.gz

endif



# compressed boot image targets (arch/mips/boot/compressed/)

bootz-y			:= vmlinuz

bootz-y			+= vmlinuz.bin

bootz-y			+= vmlinuz.ecoff

bootz-y			+= vmlinuz.srec



ifdef CONFIG_LASAT

rom.bin rom.sw: vmlinux

	$(Q)$(MAKE) $(build)=arch/mips/lasat/image $@

	$(Q)$(MAKE) $(build)=arch/mips/lasat/image \

		$(bootvars-y) $@

endif



#
@@ -280,13 +301,14 @@ vmlinux.64: vmlinux 
all:	$(all-y)



# boot

vmlinux.bin vmlinux.ecoff vmlinux.srec: $(vmlinux-32) FORCE

	$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@

$(boot-y): $(vmlinux-32) FORCE

	$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \

		$(bootvars-y) arch/mips/boot/$@



# boot/compressed

vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE

$(bootz-y): $(vmlinux-32) FORCE

	$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \

	   VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@

		$(bootvars-y) 32bit-bfd=$(32bit-bfd) $@





CLEAN_FILES += vmlinux.32 vmlinux.64
@@ -323,6 +345,8 @@ define archhelp 
	echo '  vmlinuz.ecoff        - ECOFF zboot image'

	echo '  vmlinuz.bin          - Raw binary zboot image'

	echo '  vmlinuz.srec         - SREC zboot image'

	echo '  uImage               - U-Boot image'

	echo '  uImage.gz            - U-Boot image (gzip)'

	echo

	echo '  These will be default as appropriate for a configured platform.'

endef

arch/mips/ath79/clock.c

+149 −109
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <linux/init.h>

#include <linux/err.h>

#include <linux/clk.h>

#include <linux/clkdev.h>



#include <asm/div64.h>
@@ -31,92 +32,132 @@ struct clk { 
	unsigned long rate;

};



static struct clk ath79_ref_clk;

static struct clk ath79_cpu_clk;

static struct clk ath79_ddr_clk;

static struct clk ath79_ahb_clk;

static struct clk ath79_wdt_clk;

static struct clk ath79_uart_clk;

static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)

{

	struct clk *clk;

	int err;



	clk = kzalloc(sizeof(*clk), GFP_KERNEL);

	if (!clk)

		panic("failed to allocate %s clock structure", id);



	clk->rate = rate;



	err = clk_register_clkdev(clk, id, NULL);

	if (err)

		panic("unable to register %s clock device", id);

}



static void __init ar71xx_clocks_init(void)

{

	unsigned long ref_rate;

	unsigned long cpu_rate;

	unsigned long ddr_rate;

	unsigned long ahb_rate;

	u32 pll;

	u32 freq;

	u32 div;



	ath79_ref_clk.rate = AR71XX_BASE_FREQ;

	ref_rate = AR71XX_BASE_FREQ;



	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);



	div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;

	freq = div * ath79_ref_clk.rate;

	freq = div * ref_rate;



	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;

	ath79_cpu_clk.rate = freq / div;

	cpu_rate = freq / div;



	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;

	ath79_ddr_clk.rate = freq / div;

	ddr_rate = freq / div;



	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;

	ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;

	ahb_rate = cpu_rate / div;



	ath79_add_sys_clkdev("ref", ref_rate);

	ath79_add_sys_clkdev("cpu", cpu_rate);

	ath79_add_sys_clkdev("ddr", ddr_rate);

	ath79_add_sys_clkdev("ahb", ahb_rate);



	ath79_wdt_clk.rate = ath79_ahb_clk.rate;

	ath79_uart_clk.rate = ath79_ahb_clk.rate;

	clk_add_alias("wdt", NULL, "ahb", NULL);

	clk_add_alias("uart", NULL, "ahb", NULL);

}



static void __init ar724x_clocks_init(void)

{

	unsigned long ref_rate;

	unsigned long cpu_rate;

	unsigned long ddr_rate;

	unsigned long ahb_rate;

	u32 pll;

	u32 freq;

	u32 div;



	ath79_ref_clk.rate = AR724X_BASE_FREQ;

	ref_rate = AR724X_BASE_FREQ;

	pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);



	div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);

	freq = div * ath79_ref_clk.rate;

	freq = div * ref_rate;



	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);

	freq *= div;



	ath79_cpu_clk.rate = freq;

	cpu_rate = freq;



	div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;

	ath79_ddr_clk.rate = freq / div;

	ddr_rate = freq / div;



	div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;

	ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;

	ahb_rate = cpu_rate / div;



	ath79_add_sys_clkdev("ref", ref_rate);

	ath79_add_sys_clkdev("cpu", cpu_rate);

	ath79_add_sys_clkdev("ddr", ddr_rate);

	ath79_add_sys_clkdev("ahb", ahb_rate);



	ath79_wdt_clk.rate = ath79_ahb_clk.rate;

	ath79_uart_clk.rate = ath79_ahb_clk.rate;

	clk_add_alias("wdt", NULL, "ahb", NULL);

	clk_add_alias("uart", NULL, "ahb", NULL);

}



static void __init ar913x_clocks_init(void)

{

	unsigned long ref_rate;

	unsigned long cpu_rate;

	unsigned long ddr_rate;

	unsigned long ahb_rate;

	u32 pll;

	u32 freq;

	u32 div;



	ath79_ref_clk.rate = AR913X_BASE_FREQ;

	ref_rate = AR913X_BASE_FREQ;

	pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);



	div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);

	freq = div * ath79_ref_clk.rate;

	freq = div * ref_rate;



	ath79_cpu_clk.rate = freq;

	cpu_rate = freq;



	div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;

	ath79_ddr_clk.rate = freq / div;

	ddr_rate = freq / div;



	div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;

	ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;

	ahb_rate = cpu_rate / div;



	ath79_wdt_clk.rate = ath79_ahb_clk.rate;

	ath79_uart_clk.rate = ath79_ahb_clk.rate;

	ath79_add_sys_clkdev("ref", ref_rate);

	ath79_add_sys_clkdev("cpu", cpu_rate);

	ath79_add_sys_clkdev("ddr", ddr_rate);

	ath79_add_sys_clkdev("ahb", ahb_rate);



	clk_add_alias("wdt", NULL, "ahb", NULL);

	clk_add_alias("uart", NULL, "ahb", NULL);

}



static void __init ar933x_clocks_init(void)

{

	unsigned long ref_rate;

	unsigned long cpu_rate;

	unsigned long ddr_rate;

	unsigned long ahb_rate;

	u32 clock_ctrl;

	u32 cpu_config;

	u32 freq;
@@ -124,21 +165,21 @@ static void __init ar933x_clocks_init(void) 


	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);

	if (t & AR933X_BOOTSTRAP_REF_CLK_40)

		ath79_ref_clk.rate = (40 * 1000 * 1000);

		ref_rate = (40 * 1000 * 1000);

	else

		ath79_ref_clk.rate = (25 * 1000 * 1000);

		ref_rate = (25 * 1000 * 1000);



	clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);

	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {

		ath79_cpu_clk.rate = ath79_ref_clk.rate;

		ath79_ahb_clk.rate = ath79_ref_clk.rate;

		ath79_ddr_clk.rate = ath79_ref_clk.rate;

		cpu_rate = ref_rate;

		ahb_rate = ref_rate;

		ddr_rate = ref_rate;

	} else {

		cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);



		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &

		    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;

		freq = ath79_ref_clk.rate / t;

		freq = ref_rate / t;



		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &

		    AR933X_PLL_CPU_CONFIG_NINT_MASK;
@@ -153,19 +194,24 @@ static void __init ar933x_clocks_init(void) 


		t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &

		     AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;

		ath79_cpu_clk.rate = freq / t;

		cpu_rate = freq / t;



		t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &

		      AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;

		ath79_ddr_clk.rate = freq / t;

		ddr_rate = freq / t;



		t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &

		     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;

		ath79_ahb_clk.rate = freq / t;

		ahb_rate = freq / t;

	}



	ath79_wdt_clk.rate = ath79_ref_clk.rate;

	ath79_uart_clk.rate = ath79_ref_clk.rate;

	ath79_add_sys_clkdev("ref", ref_rate);

	ath79_add_sys_clkdev("cpu", cpu_rate);

	ath79_add_sys_clkdev("ddr", ddr_rate);

	ath79_add_sys_clkdev("ahb", ahb_rate);



	clk_add_alias("wdt", NULL, "ahb", NULL);

	clk_add_alias("uart", NULL, "ref", NULL);

}



static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
@@ -174,12 +220,12 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, 
	u64 t;

	u32 ret;



	t = ath79_ref_clk.rate;

	t = ref;

	t *= nint;

	do_div(t, ref_div);

	ret = t;



	t = ath79_ref_clk.rate;

	t = ref;

	t *= nfrac;

	do_div(t, ref_div * frac);

	ret += t;
@@ -190,6 +236,10 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, 


static void __init ar934x_clocks_init(void)

{

	unsigned long ref_rate;

	unsigned long cpu_rate;

	unsigned long ddr_rate;

	unsigned long ahb_rate;

	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;

	u32 cpu_pll, ddr_pll;

	u32 bootstrap;
@@ -199,9 +249,9 @@ static void __init ar934x_clocks_init(void) 


	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);

	if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)

		ath79_ref_clk.rate = 40 * 1000 * 1000;

		ref_rate = 40 * 1000 * 1000;

	else

		ath79_ref_clk.rate = 25 * 1000 * 1000;

		ref_rate = 25 * 1000 * 1000;



	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);

	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
@@ -227,7 +277,7 @@ static void __init ar934x_clocks_init(void) 
		frac = 1 << 6;

	}



	cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,

	cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,

				      nfrac, frac, out_div);



	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
@@ -254,7 +304,7 @@ static void __init ar934x_clocks_init(void) 
		frac = 1 << 10;

	}



	ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,

	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,

				      nfrac, frac, out_div);



	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
@@ -263,49 +313,58 @@ static void __init ar934x_clocks_init(void) 
		  AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;



	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)

		ath79_cpu_clk.rate = ath79_ref_clk.rate;

		cpu_rate = ref_rate;

	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)

		ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);

		cpu_rate = cpu_pll / (postdiv + 1);

	else

		ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);

		cpu_rate = ddr_pll / (postdiv + 1);



	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &

		  AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;



	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)

		ath79_ddr_clk.rate = ath79_ref_clk.rate;

		ddr_rate = ref_rate;

	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)

		ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);

		ddr_rate = ddr_pll / (postdiv + 1);

	else

		ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);

		ddr_rate = cpu_pll / (postdiv + 1);



	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &

		  AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;



	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)

		ath79_ahb_clk.rate = ath79_ref_clk.rate;

		ahb_rate = ref_rate;

	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)

		ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);

		ahb_rate = ddr_pll / (postdiv + 1);

	else

		ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);

		ahb_rate = cpu_pll / (postdiv + 1);



	ath79_add_sys_clkdev("ref", ref_rate);

	ath79_add_sys_clkdev("cpu", cpu_rate);

	ath79_add_sys_clkdev("ddr", ddr_rate);

	ath79_add_sys_clkdev("ahb", ahb_rate);



	ath79_wdt_clk.rate = ath79_ref_clk.rate;

	ath79_uart_clk.rate = ath79_ref_clk.rate;

	clk_add_alias("wdt", NULL, "ref", NULL);

	clk_add_alias("uart", NULL, "ref", NULL);



	iounmap(dpll_base);

}



static void __init qca955x_clocks_init(void)

{

	unsigned long ref_rate;

	unsigned long cpu_rate;

	unsigned long ddr_rate;

	unsigned long ahb_rate;

	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;

	u32 cpu_pll, ddr_pll;

	u32 bootstrap;



	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);

	if (bootstrap &	QCA955X_BOOTSTRAP_REF_CLK_40)

		ath79_ref_clk.rate = 40 * 1000 * 1000;

		ref_rate = 40 * 1000 * 1000;

	else

		ath79_ref_clk.rate = 25 * 1000 * 1000;

		ref_rate = 25 * 1000 * 1000;



	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);

	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
@@ -317,8 +376,8 @@ static void __init qca955x_clocks_init(void) 
	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &

	       QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;



	cpu_pll = nint * ath79_ref_clk.rate / ref_div;

	cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));

	cpu_pll = nint * ref_rate / ref_div;

	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));

	cpu_pll /= (1 << out_div);



	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
@@ -331,8 +390,8 @@ static void __init qca955x_clocks_init(void) 
	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &

	       QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;



	ddr_pll = nint * ath79_ref_clk.rate / ref_div;

	ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));

	ddr_pll = nint * ref_rate / ref_div;

	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));

	ddr_pll /= (1 << out_div);



	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
@@ -341,34 +400,39 @@ static void __init qca955x_clocks_init(void) 
		  QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;



	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)

		ath79_cpu_clk.rate = ath79_ref_clk.rate;

		cpu_rate = ref_rate;

	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)

		ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);

		cpu_rate = ddr_pll / (postdiv + 1);

	else

		ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);

		cpu_rate = cpu_pll / (postdiv + 1);



	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &

		  QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;



	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)

		ath79_ddr_clk.rate = ath79_ref_clk.rate;

		ddr_rate = ref_rate;

	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)

		ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);

		ddr_rate = cpu_pll / (postdiv + 1);

	else

		ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);

		ddr_rate = ddr_pll / (postdiv + 1);



	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &

		  QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;



	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)

		ath79_ahb_clk.rate = ath79_ref_clk.rate;

		ahb_rate = ref_rate;

	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)

		ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);

		ahb_rate = ddr_pll / (postdiv + 1);

	else

		ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);

		ahb_rate = cpu_pll / (postdiv + 1);



	ath79_wdt_clk.rate = ath79_ref_clk.rate;

	ath79_uart_clk.rate = ath79_ref_clk.rate;

	ath79_add_sys_clkdev("ref", ref_rate);

	ath79_add_sys_clkdev("cpu", cpu_rate);

	ath79_add_sys_clkdev("ddr", ddr_rate);

	ath79_add_sys_clkdev("ahb", ahb_rate);



	clk_add_alias("wdt", NULL, "ref", NULL);

	clk_add_alias("uart", NULL, "ref", NULL);

}



void __init ath79_clocks_init(void)
@@ -387,46 +451,27 @@ void __init ath79_clocks_init(void) 
		qca955x_clocks_init();

	else

		BUG();



	pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, "

		"Ref:%lu.%03luMHz",

		ath79_cpu_clk.rate / 1000000,

		(ath79_cpu_clk.rate / 1000) % 1000,

		ath79_ddr_clk.rate / 1000000,

		(ath79_ddr_clk.rate / 1000) % 1000,

		ath79_ahb_clk.rate / 1000000,

		(ath79_ahb_clk.rate / 1000) % 1000,

		ath79_ref_clk.rate / 1000000,

		(ath79_ref_clk.rate / 1000) % 1000);

}



/*

 * Linux clock API

 */

struct clk *clk_get(struct device *dev, const char *id)

unsigned long __init

ath79_get_sys_clk_rate(const char *id)

{

	if (!strcmp(id, "ref"))

		return &ath79_ref_clk;



	if (!strcmp(id, "cpu"))

		return &ath79_cpu_clk;



	if (!strcmp(id, "ddr"))

		return &ath79_ddr_clk;



	if (!strcmp(id, "ahb"))

		return &ath79_ahb_clk;

	struct clk *clk;

	unsigned long rate;



	if (!strcmp(id, "wdt"))

		return &ath79_wdt_clk;

	clk = clk_get(NULL, id);

	if (IS_ERR(clk))

		panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));



	if (!strcmp(id, "uart"))

		return &ath79_uart_clk;

	rate = clk_get_rate(clk);

	clk_put(clk);



	return ERR_PTR(-ENOENT);

	return rate;

}

EXPORT_SYMBOL(clk_get);



/*

 * Linux clock API

 */

int clk_enable(struct clk *clk)

{

	return 0;
@@ -443,8 +488,3 @@ unsigned long clk_get_rate(struct clk *clk) 
	return clk->rate;

}

EXPORT_SYMBOL(clk_get_rate);
 


void clk_put(struct clk *clk)

{

}

EXPORT_SYMBOL(clk_put);

arch/mips/ath79/common.h

+2 −0
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ 
#define ATH79_MEM_SIZE_MAX	(128 * 1024 * 1024)



void ath79_clocks_init(void);

unsigned long ath79_get_sys_clk_rate(const char *id);



void ath79_ddr_wb_flush(unsigned int reg);



void ath79_gpio_function_enable(u32 mask);