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Commit 5a6b184a authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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clk: tegra: Use common definition of APBDMA clock gate 



The APBDMA clock is defined in the common clock gates table that is used
by Tegra30+. Tegra20 can use it too, let's remove the custom definition
and use the common one.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3ff46fd0

drivers/clk/tegra/clk-tegra20.c

+1 −5
Original line number Diff line number Diff line
@@ -523,6 +523,7 @@ static struct tegra_devclk devclks[] __initdata = { 


static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {

	[tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },

	[tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true },

	[tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },

	[tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },

	[tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
@@ -807,11 +808,6 @@ static void __init tegra20_periph_clk_init(void) 
				    clk_base, 0, 3, periph_clk_enb_refcnt);

	clks[TEGRA20_CLK_AC97] = clk;



	/* apbdma */

	clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,

				    0, 34, periph_clk_enb_refcnt);

	clks[TEGRA20_CLK_APBDMA] = clk;



	/* emc */

	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,

			       ARRAY_SIZE(mux_pllmcp_clkm),