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Commit 59d711e9 authored by Andrew Bresticker's avatar Andrew Bresticker Committed by Tomasz Figa
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ARM: dts: exynos5420: add input clocks to audss clock controller 



Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in)
for the AudioSS clock controller.

Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Acked-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
parent 3538a2cf

arch/arm/boot/dts/exynos5420.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -76,8 +76,8 @@ 
		compatible = "samsung,exynos5420-audss-clock";

		reg = <0x03810000 0x0C>;

		#clock-cells = <1>;

		clocks = <&clock 148>;

		clock-names = "sclk_audio";

		clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;

		clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";

	};



	codec@11000000 {