Loading Documentation/devicetree/bindings/clock/qcom,camcc.txt +1 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,7 @@ Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding Required properties : - compatible: must contain "qcom,camcc-sm8150", "qcom,camcc-sm8150-v2" , "qcom,camcc-kona" or "qcom,camcc-lito". , "qcom,camcc-kona" or "qcom,lito-camcc". - reg: shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. Loading Documentation/devicetree/bindings/clock/qcom,videocc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -3,6 +3,7 @@ Qualcomm Video Clock & Reset Controller Binding Required properties : - compatible : shall contain "qcom,sdm845-videocc" or "qcom,kona-videocc" or "qcom,lito-videocc" - reg : shall contain base register location and length - clock-names : Shall contain "cfg_ahb_clk" - clocks : phandle + clock reference to the GCC AHB clock. Loading include/dt-bindings/clock/qcom,videocc-lito.h +3 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_LITO_H #define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_LITO_H Loading @@ -16,6 +16,8 @@ #define VIDEO_CC_XO_CLK 9 #define VIDEO_CC_XO_CLK_SRC 10 #define VIDEO_CC_APB_CLK 11 #define VIDEO_CC_SLEEP_CLK 12 #define VIDEO_CC_SLEEP_CLK_SRC 13 #define VIDEO_CC_INTERFACE_BCR 0 #define VIDEO_CC_MVS0_BCR 1 Loading Loading
Documentation/devicetree/bindings/clock/qcom,camcc.txt +1 −1 Original line number Diff line number Diff line Loading @@ -3,7 +3,7 @@ Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding Required properties : - compatible: must contain "qcom,camcc-sm8150", "qcom,camcc-sm8150-v2" , "qcom,camcc-kona" or "qcom,camcc-lito". , "qcom,camcc-kona" or "qcom,lito-camcc". - reg: shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. Loading
Documentation/devicetree/bindings/clock/qcom,videocc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -3,6 +3,7 @@ Qualcomm Video Clock & Reset Controller Binding Required properties : - compatible : shall contain "qcom,sdm845-videocc" or "qcom,kona-videocc" or "qcom,lito-videocc" - reg : shall contain base register location and length - clock-names : Shall contain "cfg_ahb_clk" - clocks : phandle + clock reference to the GCC AHB clock. Loading
include/dt-bindings/clock/qcom,videocc-lito.h +3 −1 Original line number Diff line number Diff line /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_LITO_H #define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_LITO_H Loading @@ -16,6 +16,8 @@ #define VIDEO_CC_XO_CLK 9 #define VIDEO_CC_XO_CLK_SRC 10 #define VIDEO_CC_APB_CLK 11 #define VIDEO_CC_SLEEP_CLK 12 #define VIDEO_CC_SLEEP_CLK_SRC 13 #define VIDEO_CC_INTERFACE_BCR 0 #define VIDEO_CC_MVS0_BCR 1 Loading