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Commit 59879d54 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm/book3s64: Move book3s64 code to pgtable-book3s64 



Only code movement and avoid #ifdef.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent a42ae34f

arch/powerpc/mm/pgtable-book3s64.c

+54 −0
Original line number Diff line number Diff line
@@ -9,10 +9,13 @@ 


#include <linux/sched.h>

#include <linux/mm_types.h>

#include <linux/memblock.h>

#include <misc/cxl-base.h>



#include <asm/pgalloc.h>

#include <asm/tlb.h>

#include <asm/trace.h>

#include <asm/powernv.h>



#include "mmu_decl.h"

#include <trace/events/thp.h>
@@ -171,3 +174,54 @@ int __meminit remove_section_mapping(unsigned long start, unsigned long end) 
	return hash__remove_section_mapping(start, end);

}

#endif /* CONFIG_MEMORY_HOTPLUG */



void __init mmu_partition_table_init(void)

{

	unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;

	unsigned long ptcr;



	BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 36), "Partition table size too large.");

	partition_tb = __va(memblock_alloc_base(patb_size, patb_size,

						MEMBLOCK_ALLOC_ANYWHERE));



	/* Initialize the Partition Table with no entries */

	memset((void *)partition_tb, 0, patb_size);



	/*

	 * update partition table control register,

	 * 64 K size.

	 */

	ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12);

	mtspr(SPRN_PTCR, ptcr);

	powernv_set_nmmu_ptcr(ptcr);

}



void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,

				   unsigned long dw1)

{

	unsigned long old = be64_to_cpu(partition_tb[lpid].patb0);



	partition_tb[lpid].patb0 = cpu_to_be64(dw0);

	partition_tb[lpid].patb1 = cpu_to_be64(dw1);



	/*

	 * Global flush of TLBs and partition table caches for this lpid.

	 * The type of flush (hash or radix) depends on what the previous

	 * use of this partition ID was, not the new use.

	 */

	asm volatile("ptesync" : : : "memory");

	if (old & PATB_HR) {

		asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :

			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));

		asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :

			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));

		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);

	} else {

		asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :

			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));

		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);

	}

	/* do we need fixup here ?*/

	asm volatile("eieio; tlbsync; ptesync" : : : "memory");

}

EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry);

arch/powerpc/mm/pgtable_64.c

+0 −56
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 
#include <linux/swap.h>

#include <linux/stddef.h>

#include <linux/vmalloc.h>

#include <linux/memblock.h>

#include <linux/slab.h>

#include <linux/hugetlb.h>
@@ -47,13 +46,11 @@ 
#include <asm/smp.h>

#include <asm/machdep.h>

#include <asm/tlb.h>

#include <asm/trace.h>

#include <asm/processor.h>

#include <asm/cputable.h>

#include <asm/sections.h>

#include <asm/firmware.h>

#include <asm/dma.h>

#include <asm/powernv.h>



#include "mmu_decl.h"
@@ -429,59 +426,6 @@ void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift) 
}

#endif



#ifdef CONFIG_PPC_BOOK3S_64

void __init mmu_partition_table_init(void)

{

	unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;

	unsigned long ptcr;



	BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 36), "Partition table size too large.");

	partition_tb = __va(memblock_alloc_base(patb_size, patb_size,

						MEMBLOCK_ALLOC_ANYWHERE));



	/* Initialize the Partition Table with no entries */

	memset((void *)partition_tb, 0, patb_size);



	/*

	 * update partition table control register,

	 * 64 K size.

	 */

	ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12);

	mtspr(SPRN_PTCR, ptcr);

	powernv_set_nmmu_ptcr(ptcr);

}



void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,

				   unsigned long dw1)

{

	unsigned long old = be64_to_cpu(partition_tb[lpid].patb0);



	partition_tb[lpid].patb0 = cpu_to_be64(dw0);

	partition_tb[lpid].patb1 = cpu_to_be64(dw1);



	/*

	 * Global flush of TLBs and partition table caches for this lpid.

	 * The type of flush (hash or radix) depends on what the previous

	 * use of this partition ID was, not the new use.

	 */

	asm volatile("ptesync" : : : "memory");

	if (old & PATB_HR) {

		asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :

			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));

		asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :

			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));

		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);

	} else {

		asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :

			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));

		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);

	}

	/* do we need fixup here ?*/

	asm volatile("eieio; tlbsync; ptesync" : : : "memory");

}

EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry);

#endif /* CONFIG_PPC_BOOK3S_64 */



#ifdef CONFIG_STRICT_KERNEL_RWX

void mark_rodata_ro(void)

{