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Commit 5958b699 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.19.289 into android-4.19-stable 



Changes in 4.19.289
	x86/microcode/AMD: Load late on both threads too
	x86/cpu/amd: Move the errata checking functionality up
	x86/cpu/amd: Add a Zenbleed fix
	Linux 4.19.289

Change-Id: Ib71b14444b7b3da46ebdcfc747f9dd9d9e1c5ccf
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents f13140b2 767049ce

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 19

SUBLEVEL = 288

SUBLEVEL = 289

EXTRAVERSION =

NAME = "People's Front"

arch/x86/include/asm/microcode.h

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#include <asm/cpu.h>

#include <linux/earlycpio.h>

#include <linux/initrd.h>

#include <asm/microcode_amd.h>



struct ucode_patch {

	struct list_head plist;

arch/x86/include/asm/microcode_amd.h

+2 −0
Original line number Diff line number Diff line
@@ -48,11 +48,13 @@ extern void __init load_ucode_amd_bsp(unsigned int family); 
extern void load_ucode_amd_ap(unsigned int family);

extern int __init save_microcode_in_initrd_amd(unsigned int family);

void reload_ucode_amd(unsigned int cpu);

extern void amd_check_microcode(void);

#else

static inline void __init load_ucode_amd_bsp(unsigned int family) {}

static inline void load_ucode_amd_ap(unsigned int family) {}

static inline int __init

save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }

static inline void reload_ucode_amd(unsigned int cpu) {}

static inline void amd_check_microcode(void) {}

#endif

#endif /* _ASM_X86_MICROCODE_AMD_H */

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -407,6 +407,7 @@ 
#define MSR_AMD64_DE_CFG		0xc0011029

#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT	 1

#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE	BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)

#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9



#define MSR_AMD64_BU_CFG2		0xc001102a

#define MSR_AMD64_IBSFETCHCTL		0xc0011030

arch/x86/kernel/cpu/amd.c

+127 −72
Original line number Diff line number Diff line
@@ -23,11 +23,6 @@ 


#include "cpu.h"



static const int amd_erratum_383[];

static const int amd_erratum_400[];

static const int amd_erratum_1054[];

static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);



/*

 * nodes_per_socket: Stores the number of nodes per socket.

 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
@@ -35,6 +30,78 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 
 */

static u32 nodes_per_socket = 1;



/*

 * AMD errata checking

 *

 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or

 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that

 * have an OSVW id assigned, which it takes as first argument. Both take a

 * variable number of family-specific model-stepping ranges created by

 * AMD_MODEL_RANGE().

 *

 * Example:

 *

 * const int amd_erratum_319[] =

 *	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),

 *			   AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),

 *			   AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));

 */



#define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }

#define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }

#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \

	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))

#define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)

#define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)

#define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)



static const int amd_erratum_400[] =

	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),

			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));



static const int amd_erratum_383[] =

	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));



/* #1054: Instructions Retired Performance Counter May Be Inaccurate */

static const int amd_erratum_1054[] =

	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));



static const int amd_zenbleed[] =

	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),

			   AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),

			   AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));



static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)

{

	int osvw_id = *erratum++;

	u32 range;

	u32 ms;



	if (osvw_id >= 0 && osvw_id < 65536 &&

	    cpu_has(cpu, X86_FEATURE_OSVW)) {

		u64 osvw_len;



		rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);

		if (osvw_id < osvw_len) {

			u64 osvw_bits;



			rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),

			    osvw_bits);

			return osvw_bits & (1ULL << (osvw_id & 0x3f));

		}

	}



	/* OSVW unavailable or ID unknown, match family-model-stepping range */

	ms = (cpu->x86_model << 4) | cpu->x86_stepping;

	while ((range = *erratum++))

		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&

		    (ms >= AMD_MODEL_RANGE_START(range)) &&

		    (ms <= AMD_MODEL_RANGE_END(range)))

			return true;



	return false;

}



static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)

{

	u32 gprs[8] = { 0 };
@@ -909,6 +976,47 @@ static void init_amd_zn(struct cpuinfo_x86 *c) 
	}

}



static bool cpu_has_zenbleed_microcode(void)

{

	u32 good_rev = 0;



	switch (boot_cpu_data.x86_model) {

	case 0x30 ... 0x3f: good_rev = 0x0830107a; break;

	case 0x60 ... 0x67: good_rev = 0x0860010b; break;

	case 0x68 ... 0x6f: good_rev = 0x08608105; break;

	case 0x70 ... 0x7f: good_rev = 0x08701032; break;

	case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;



	default:

		return false;

		break;

	}



	if (boot_cpu_data.microcode < good_rev)

		return false;



	return true;

}



static void zenbleed_check(struct cpuinfo_x86 *c)

{

	if (!cpu_has_amd_erratum(c, amd_zenbleed))

		return;



	if (cpu_has(c, X86_FEATURE_HYPERVISOR))

		return;



	if (!cpu_has(c, X86_FEATURE_AVX))

		return;



	if (!cpu_has_zenbleed_microcode()) {

		pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");

		msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);

	} else {

		msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);

	}

}



static void init_amd(struct cpuinfo_x86 *c)

{

	early_init_amd(c);
@@ -1011,6 +1119,8 @@ static void init_amd(struct cpuinfo_x86 *c) 
		msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);



	check_null_seg_clears_base(c);



	zenbleed_check(c);

}



#ifdef CONFIG_X86_32
@@ -1106,73 +1216,6 @@ static const struct cpu_dev amd_cpu_dev = { 


cpu_dev_register(amd_cpu_dev);



/*

 * AMD errata checking

 *

 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or

 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that

 * have an OSVW id assigned, which it takes as first argument. Both take a

 * variable number of family-specific model-stepping ranges created by

 * AMD_MODEL_RANGE().

 *

 * Example:

 *

 * const int amd_erratum_319[] =

 *	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),

 *			   AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),

 *			   AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));

 */



#define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }

#define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }

#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \

	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))

#define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)

#define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)

#define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)



static const int amd_erratum_400[] =

	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),

			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));



static const int amd_erratum_383[] =

	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));



/* #1054: Instructions Retired Performance Counter May Be Inaccurate */

static const int amd_erratum_1054[] =

	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));



static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)

{

	int osvw_id = *erratum++;

	u32 range;

	u32 ms;



	if (osvw_id >= 0 && osvw_id < 65536 &&

	    cpu_has(cpu, X86_FEATURE_OSVW)) {

		u64 osvw_len;



		rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);

		if (osvw_id < osvw_len) {

			u64 osvw_bits;



			rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),

			    osvw_bits);

			return osvw_bits & (1ULL << (osvw_id & 0x3f));

		}

	}



	/* OSVW unavailable or ID unknown, match family-model-stepping range */

	ms = (cpu->x86_model << 4) | cpu->x86_stepping;

	while ((range = *erratum++))

		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&

		    (ms >= AMD_MODEL_RANGE_START(range)) &&

		    (ms <= AMD_MODEL_RANGE_END(range)))

			return true;



	return false;

}



void set_dr_addr_mask(unsigned long mask, int dr)

{

	if (!boot_cpu_has(X86_FEATURE_BPEXT))
@@ -1191,3 +1234,15 @@ void set_dr_addr_mask(unsigned long mask, int dr) 
		break;

	}

}



static void zenbleed_check_cpu(void *unused)

{

	struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());



	zenbleed_check(c);

}



void amd_check_microcode(void)

{

	on_each_cpu(zenbleed_check_cpu, NULL, 1);

}