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Commit 593e59b4 authored by Zhao Yan's avatar Zhao Yan Committed by Zhenyu Wang
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drm/i915/gvt: fix unhandled mmio warnings 



some registers were missing or treated as BDW only. This patch is to fix it
avoid unhandled mmio wanrings

v2: update commit message according to zhenyu's comment

Signed-off-by: default avatarZhao Yan <yan.y.zhao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 9272f73f

drivers/gpu/drm/i915/gvt/handlers.c

+11 −4
Original line number Diff line number Diff line
@@ -1519,6 +1519,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL);

	MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL);

	MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK, NULL, NULL);

	MMIO_DFH(0x2124, D_ALL, F_MODE_MASK, NULL, NULL);



	MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL);

	MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL);
@@ -2390,9 +2392,9 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) 


	MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);



	MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW);

	MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW);

	MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW);

	MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);

	MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);

	MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);



	MMIO_D(WM_MISC, D_BDW);

	MMIO_D(BDW_EDP_PSR_BASE, D_BDW);
@@ -2406,7 +2408,7 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);

	MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);



	MMIO_D(0xfdc, D_BDW);

	MMIO_D(0xfdc, D_BDW_PLUS);

	MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS);

	MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS);
@@ -2423,6 +2425,10 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) 
	MMIO_DFH(0x24d8, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x24dc, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);



	MMIO_D(0x22040, D_BDW_PLUS);

	MMIO_D(0x44484, D_BDW_PLUS);

	MMIO_D(0x4448c, D_BDW_PLUS);



	MMIO_D(0x83a4, D_BDW);

	MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
@@ -2668,6 +2674,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL);



	MMIO_D(0x44500, D_SKL);

	MMIO_D(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS);

	return 0;

}