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Commit 58f0ac98 authored by Greg Ungerer's avatar Greg Ungerer
Browse files

m68knommu: remove use of MBAR in old-style ColdFire timer 



Not all ColdFire CPUs that use the old style timer hardware module use
an MBAR set peripheral region. Move the TIMER base address defines to the
per-CPU header files where we can set it correctly based on how the
peripherals are mapped - instead of using a fake MBAR for some platforms.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent babc08b7

arch/m68k/include/asm/m5206sim.h

+3 −0
Original line number Diff line number Diff line
@@ -89,6 +89,9 @@ 
#define	MCFSIM_PAR		0xcb		/* Pin Assignment reg (r/w) */

#endif



#define	MCFTIMER_BASE1		(MCF_MBAR + 0x100)	/* Base of TIMER1 */

#define	MCFTIMER_BASE2		(MCF_MBAR + 0x120)	/* Base of TIMER2 */



#define	MCFSIM_PADDR		(MCF_MBAR + 0x1c5)	/* Parallel Direction (r/w) */

#define	MCFSIM_PADAT		(MCF_MBAR + 0x1c9)	/* Parallel Port Value (r/w) */

arch/m68k/include/asm/m5249sim.h

+7 −1
Original line number Diff line number Diff line
@@ -66,6 +66,12 @@ 
#define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */

#define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */



/*

 *	Timer module.

 */

#define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */

#define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */



/*

 *	UART module.

 */

arch/m68k/include/asm/m5272sim.h

+5 −0
Original line number Diff line number Diff line
@@ -82,6 +82,11 @@ 


#define	MCFDMA_BASE0		(MCF_MBAR + 0xe0) /* Base address DMA 0 */



#define	MCFTIMER_BASE1		(MCF_MBAR + 0x200) /* Base address TIMER1 */

#define	MCFTIMER_BASE2		(MCF_MBAR + 0x220) /* Base address TIMER2 */

#define	MCFTIMER_BASE3		(MCF_MBAR + 0x240) /* Base address TIMER4 */

#define	MCFTIMER_BASE4		(MCF_MBAR + 0x260) /* Base address TIMER3 */



/*

 *	Define system peripheral IRQ usage.

 */

arch/m68k/include/asm/m5307sim.h

+6 −0
Original line number Diff line number Diff line
@@ -95,6 +95,12 @@ 
#define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */

#define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */



/*

 *  Timer module.

 */

#define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */

#define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */



#define	MCFSIM_PADDR		(MCF_MBAR + 0x244)

#define	MCFSIM_PADAT		(MCF_MBAR + 0x248)

arch/m68k/include/asm/m532xsim.h

+8 −0
Original line number Diff line number Diff line
@@ -85,6 +85,14 @@ 
#define MCFUART_BASE2		0xFC064000	/* Base address of UART2 */

#define MCFUART_BASE3		0xFC068000	/* Base address of UART3 */



/*

 *  Timer module.

 */

#define MCFTIMER_BASE1		0xFC070000	/* Base address of TIMER1 */

#define MCFTIMER_BASE2		0xFC074000	/* Base address of TIMER2 */

#define MCFTIMER_BASE3		0xFC078000	/* Base address of TIMER3 */

#define MCFTIMER_BASE4		0xFC07C000	/* Base address of TIMER4 */



/*********************************************************************

 *

 * Reset Controller Module