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Commit 58dcfb3a authored by Anand Gadiyar's avatar Anand Gadiyar Committed by Tony Lindgren
Browse files

omap: 3630: disable TLL SAR on 3630 ES1 



USBTLL Save-and-Restore is broken in 3630 ES1.0. Having it
enabled could result in incorrect register restores as
the OMAP exits off-mode. This could potentially result in
unexpected wakeup events.

(Refer 3630 errata ID i579)

This is fixed in ES1.1. So disable it for ES1.0s.

Signed-off-by: default avatarAnand Gadiyar <gadiyar@ti.com>
Acked-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent b0a1a6ce

arch/arm/mach-omap2/powerdomains34xx.h

+10 −2
Original line number Diff line number Diff line
@@ -75,12 +75,19 @@ static struct powerdomain mpu_3xxx_pwrdm = { 
	},

};



/*

 * The USBTLL Save-and-Restore mechanism is broken on

 * 3430s upto ES3.0 and 3630ES1.0. Hence this feature

 * needs to be disabled on these chips.

 * Refer: 3430 errata ID i459 and 3630 errata ID i579

 */

static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {

	.name		  = "core_pwrdm",

	.prcm_offs	  = CORE_MOD,

	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |

					   CHIP_IS_OMAP3430ES2 |

					   CHIP_IS_OMAP3430ES3_0),

					   CHIP_IS_OMAP3430ES3_0 |

					   CHIP_IS_OMAP3630ES1),

	.pwrsts		  = PWRSTS_OFF_RET_ON,

	.pwrsts_logic_ret = PWRSTS_OFF_RET,

	.banks		  = 2,
@@ -97,7 +104,8 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { 
static struct powerdomain core_3xxx_es3_1_pwrdm = {

	.name		  = "core_pwrdm",

	.prcm_offs	  = CORE_MOD,

	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),

	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |

					  CHIP_GE_OMAP3630ES1_1),

	.pwrsts		  = PWRSTS_OFF_RET_ON,

	.pwrsts_logic_ret = PWRSTS_OFF_RET,

	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */