Merge "ARM: dts: msm: Add QUPV3 i2c dt node for lito" (58b6916c) · Commits · e / devices / android_kernel_fairphone_FP4

qcom/lito-pinctrl.dtsi

+321 −0

Original line number	Diff line number	Diff line
		@@ -757,5 +757,326 @@
		output-low;
		};
		};

		/* QUPv3_0 North SE mappings */
		/* SE 0 pin mappings */
		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
		qupv3_se0_i2c_active: qupv3_se0_i2c_active {
		mux {
		pins = "gpio42", "gpio43";
		function = "qup00";
		};

		config {
		pins = "gpio42", "gpio43";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
		mux {
		pins = "gpio42", "gpio43";
		function = "gpio";
		};

		config {
		pins = "gpio42", "gpio43";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* SE 1 pin mappings */
		qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
		qupv3_se1_i2c_active: qupv3_se1_i2c_active {
		mux {
		pins = "gpio0", "gpio1";
		function = "qup01";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
		mux {
		pins = "gpio0", "gpio1";
		function = "gpio";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* SE 2 pin mappings */
		qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
		qupv3_se2_i2c_active: qupv3_se2_i2c_active {
		mux {
		pins = "gpio34", "gpio35";
		function = "qup02";
		};

		config {
		pins = "gpio34", "gpio35";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
		mux {
		pins = "gpio34", "gpio35";
		function = "gpio";
		};

		config {
		pins = "gpio34", "gpio35";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* SE 4 pin mappings */
		qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
		qupv3_se4_i2c_active: qupv3_se4_i2c_active {
		mux {
		pins = "gpio31", "gpio32";
		function = "qup04";
		};

		config {
		pins = "gpio31", "gpio32";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
		mux {
		pins = "gpio31", "gpio32";
		function = "gpio";
		};

		config {
		pins = "gpio31", "gpio32";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* SE 5 pin mappings */
		qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
		qupv3_se5_i2c_active: qupv3_se5_i2c_active {
		mux {
		pins = "gpio38", "gpio39";
		function = "qup05";
		};

		config {
		pins = "gpio38", "gpio39";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
		mux {
		pins = "gpio38", "gpio39";
		function = "gpio";
		};

		config {
		pins = "gpio38", "gpio39";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* QUPv3_1 South_1 SE mappings */
		/* SE 6 pin mappings */
		qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
		qupv3_se6_i2c_active: qupv3_se6_i2c_active {
		mux {
		pins = "gpio59", "gpio60";
		function = "qup10";
		};

		config {
		pins = "gpio59", "gpio60";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
		mux {
		pins = "gpio59", "gpio60";
		function = "gpio";
		};

		config {
		pins = "gpio59", "gpio60";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* SE 7 pin mappings */
		qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
		qupv3_se7_i2c_active: qupv3_se7_i2c_active {
		mux {
		pins = "gpio6", "gpio7";
		function = "qup11";
		};

		config {
		pins = "gpio6", "gpio7";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
		mux {
		pins = "gpio6", "gpio7";
		function = "gpio";
		};

		config {
		pins = "gpio6", "gpio7";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* SE 8 pin mappings */
		qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
		qupv3_se8_i2c_active: qupv3_se8_i2c_active {
		mux {
		pins = "gpio49", "gpio50";
		function = "qup12";
		};

		config {
		pins = "gpio49", "gpio50";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
		mux {
		pins = "gpio49", "gpio50";
		function = "gpio";
		};

		config {
		pins = "gpio49", "gpio50";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* SE 9 pin mappings */
		qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
		qupv3_se9_i2c_active: qupv3_se9_i2c_active {
		mux {
		pins = "gpio46", "gpio47";
		function = "qup13";
		};

		config {
		pins = "gpio46", "gpio47";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
		mux {
		pins = "gpio46", "gpio47";
		function = "gpio";
		};

		config {
		pins = "gpio46", "gpio47";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* SE 10 pin mappings */
		qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
		qupv3_se10_i2c_active: qupv3_se10_i2c_active {
		mux {
		pins = "gpio53", "gpio54";
		function = "qup14";
		};

		config {
		pins = "gpio53", "gpio54";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
		mux {
		pins = "gpio53", "gpio54";
		function = "gpio";
		};

		config {
		pins = "gpio53", "gpio54";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};

		/* SE 11 pin mappings */
		qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
		qupv3_se11_i2c_active: qupv3_se11_i2c_active {
		mux {
		pins = "gpio108", "gpio109";
		function = "qup15";
		};

		config {
		pins = "gpio108", "gpio109";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
		mux {
		pins = "gpio108", "gpio109";
		function = "gpio";
		};

		config {
		pins = "gpio108", "gpio109";
		drive-strength = <2>;
		bias-no-pull;
		};
		};
		};
		};
		};

qcom/lito-qupv3.dtsi

+239 −3

Original line number	Diff line number	Diff line
		#include <dt-bindings/msm/msm-bus-ids.h>

		&soc {
		/QUPv3_0 /
		/* QUPv3 North Instances
		* North 0 : SE 0
		* North 1 : SE 1
		* North 2 : SE 2
		* North 4 : SE 4
		* North 5 : SE 5
		*/

		qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x8c0000 0x2000>;
		@@ -69,12 +76,120 @@
		status = "disabled";
		};

		/QUPv3_1 /
		/* I2C */
		qupv3_se0_i2c: i2c@880000 {
		compatible = "qcom,i2c-geni";
		reg = <0x880000 0x4000>;
		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 0 3 64 0>,
		<&gpi_dma0 1 0 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_i2c_active>;
		pinctrl-1 = <&qupv3_se0_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se1_i2c: i2c@884000 {
		compatible = "qcom,i2c-geni";
		reg = <0x884000 0x4000>;
		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 1 3 64 0>,
		<&gpi_dma0 1 1 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se1_i2c_active>;
		pinctrl-1 = <&qupv3_se1_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se2_i2c: i2c@888000 {
		compatible = "qcom,i2c-geni";
		reg = <0x888000 0x4000>;
		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 2 3 64 0>,
		<&gpi_dma0 1 2 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_i2c_active>;
		pinctrl-1 = <&qupv3_se2_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se4_i2c: i2c@890000 {
		compatible = "qcom,i2c-geni";
		reg = <0x890000 0x4000>;
		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 4 3 64 0>,
		<&gpi_dma0 1 4 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se4_i2c_active>;
		pinctrl-1 = <&qupv3_se4_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se5_i2c: i2c@894000 {
		compatible = "qcom,i2c-geni";
		reg = <0x894000 0x4000>;
		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 5 3 64 0>,
		<&gpi_dma0 1 5 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_i2c_active>;
		pinctrl-1 = <&qupv3_se5_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		/* QUPv3 South_1 Instances
		* South_1 0 : SE 6
		* South_1 1 : SE 7
		* South_1 2 : SE 8
		* South_1 3 : SE 9
		* South_1 4 : SE 10
		* South_1 5 : SE 11
		*/
		qupv3_1: qcom,qupv3_1_geni_se@9c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x9c0000 0x2000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH1>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		iommus = <&apps_smmu 0x023 0x0>;
		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
		qcom,iommu-dma = "bypass";
		@@ -115,4 +230,125 @@
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		/* I2C */
		qupv3_se6_i2c: i2c@980000 {
		compatible = "qcom,i2c-geni";
		reg = <0x980000 0x4000>;
		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 0 3 64 0>,
		<&gpi_dma1 1 0 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_i2c_active>;
		pinctrl-1 = <&qupv3_se6_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se7_i2c: i2c@984000 {
		compatible = "qcom,i2c-geni";
		reg = <0x984000 0x4000>;
		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 1 3 64 0>,
		<&gpi_dma1 1 1 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_i2c_active>;
		pinctrl-1 = <&qupv3_se7_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se8_i2c: i2c@988000 {
		compatible = "qcom,i2c-geni";
		reg = <0x988000 0x4000>;
		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 2 3 64 0>,
		<&gpi_dma1 1 2 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_i2c_active>;
		pinctrl-1 = <&qupv3_se8_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se9_i2c: i2c@98c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x98c000 0x4000>;
		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 3 3 64 0>,
		<&gpi_dma1 1 3 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se9_i2c_active>;
		pinctrl-1 = <&qupv3_se9_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se10_i2c: i2c@990000 {
		compatible = "qcom,i2c-geni";
		reg = <0x990000 0x4000>;
		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 4 3 64 0>,
		<&gpi_dma1 1 4 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_i2c_active>;
		pinctrl-1 = <&qupv3_se10_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se11_i2c: i2c@994000 {
		compatible = "qcom,i2c-geni";
		reg = <0x994000 0x4000>;
		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 5 3 64 0>,
		<&gpi_dma1 1 5 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se11_i2c_active>;
		pinctrl-1 = <&qupv3_se11_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};
		};