Loading qcom/kona-sde-display.dtsi +14 −2 Original line number Diff line number Diff line Loading @@ -173,20 +173,26 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll PCLK_SRC_0_CLK>, <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>, <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll PCLK_SRC_1_CLK>, <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>, <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1", "shadow_byte_clk1", "shadow_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; Loading Loading @@ -215,10 +221,16 @@ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; <&mdss_dsi1_pll PCLK_MUX_1_CLK>, <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1"; "cphy_byte_clk0", "cphy_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; Loading Loading
qcom/kona-sde-display.dtsi +14 −2 Original line number Diff line number Diff line Loading @@ -173,20 +173,26 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll PCLK_SRC_0_CLK>, <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>, <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll PCLK_SRC_1_CLK>, <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>, <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "src_byte_clk0", "src_pixel_clk0", "cphy_byte_clk0", "cphy_pixel_clk0", "shadow_byte_clk0", "shadow_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", "src_byte_clk1", "src_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1", "shadow_byte_clk1", "shadow_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; Loading Loading @@ -215,10 +221,16 @@ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; <&mdss_dsi1_pll PCLK_MUX_1_CLK>, <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk0", "mux_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1"; "cphy_byte_clk0", "cphy_pixel_clk0", "mux_byte_clk1", "mux_pixel_clk1", "cphy_byte_clk1", "cphy_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; Loading