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Commit 5800790a authored by Shawn Lin's avatar Shawn Lin Committed by Bjorn Helgaas
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PCI: rockchip: Set vendor ID from local core config space 



The TRM says the vendor ID in the RC's configure space can be rewritten
and the value must be the same as the value read from the local core
configure space.  But we misread that and didn't notice it before.  Actually
we should only able to rewrite it from the local core configure space.

Fix that issue to make lspci show the correct IP vendor infomation.

Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent f1d722b6

drivers/pci/host/pcie-rockchip.c

+2 −2
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ 
#define   PCIE_CORE_INT_CT			BIT(11)

#define   PCIE_CORE_INT_UTC			BIT(18)

#define   PCIE_CORE_INT_MMVC			BIT(19)

#define PCIE_CORE_CONFIG_VENDOR		(PCIE_CORE_CTRL_MGMT_BASE + 0x44)

#define PCIE_CORE_INT_MASK		(PCIE_CORE_CTRL_MGMT_BASE + 0x210)

#define PCIE_RC_BAR_CONF		(PCIE_CORE_CTRL_MGMT_BASE + 0x300)
@@ -138,7 +139,6 @@ 
		 PCIE_CORE_INT_MMVC)



#define PCIE_RC_CONFIG_BASE		0xa00000

#define PCIE_RC_CONFIG_VENDOR		(PCIE_RC_CONFIG_BASE + 0x00)

#define PCIE_RC_CONFIG_RID_CCR		(PCIE_RC_CONFIG_BASE + 0x08)

#define   PCIE_RC_CONFIG_SCC_SHIFT		16

#define PCIE_RC_CONFIG_DCR		(PCIE_RC_CONFIG_BASE + 0xc4)
@@ -637,7 +637,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 
	dev_dbg(dev, "current link width is x%d\n", status);



	rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,

			    PCIE_RC_CONFIG_VENDOR);

			    PCIE_CORE_CONFIG_VENDOR);

	rockchip_pcie_write(rockchip,

			    PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,

			    PCIE_RC_CONFIG_RID_CCR);