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Commit 57f0a7ea authored by Kumar Gala's avatar Kumar Gala Committed by Olof Johansson
Browse files

arm64: dts: Add Qualcomm MSM8916 SoC and evaluation board dts 



Add initial device tree support for Qualcomm MSM8916 SoC and MTP8916
evaluation board.  At the current time we only boot up a single processor.

Signed-off-by: default avatarKumar Gala <galak@codeaurora.org>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 3341ada4

arch/arm64/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ dts-dirs += cavium 
dts-dirs += exynos

dts-dirs += freescale

dts-dirs += mediatek

dts-dirs += qcom

dts-dirs += sprd

dts-dirs += xilinx

arch/arm64/boot/dts/qcom/Makefile

0 → 100644
+5 −0
Original line number Diff line number Diff line 
dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb



always		:= $(dtb-y)

subdir-y	:= $(dts-dirs)

clean-files	:= *.dtb

arch/arm64/boot/dts/qcom/msm8916-mtp.dts

0 → 100644
+22 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/dts-v1/;



#include "msm8916-mtp.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. MSM 8916 MTP";

	compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",

			"qcom,msm8916", "qcom,mtp";

};

arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi

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+33 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include "msm8916.dtsi"



/ {

	aliases {

		serial0 = &blsp1_uart2;

	};



	chosen {

		stdout-path = "serial0";

	};



	soc {

		serial@78b0000 {

			status = "okay";

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&blsp1_uart2_default>;

			pinctrl-1 = <&blsp1_uart2_sleep>;

		};

	};

};

arch/arm64/boot/dts/qcom/msm8916.dtsi

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+196 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-msm8916.h>

#include <dt-bindings/reset/qcom,gcc-msm8916.h>



/ {

	model = "Qualcomm Technologies, Inc. MSM8916";

	compatible = "qcom,msm8916";



	interrupt-parent = <&intc>;



	#address-cells = <2>;

	#size-cells = <2>;



	aliases { };



	chosen { };



	memory {

		device_type = "memory";

		/* We expect the bootloader to fill in the reg */

		reg = <0 0 0 0>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0>;

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x1>;

		};



		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x2>;

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x3>;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	soc: soc {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0 0xffffffff>;

		compatible = "simple-bus";



		pinctrl@1000000 {

			compatible = "qcom,msm8916-pinctrl";

			reg = <0x1000000 0x300000>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;



			blsp1_uart2_default: blsp1_uart2_default {

				pinmux {

					function = "blsp_uart2";

					pins = "gpio4", "gpio5";

				};

				pinconf {

					pins = "gpio4", "gpio5";

					drive-strength = <16>;

					bias-disable;

				};

			};



			blsp1_uart2_sleep: blsp1_uart2_sleep {

				pinmux {

					function = "blsp_uart2";

					pins = "gpio4", "gpio5";

				};

				pinconf {

					pins = "gpio4", "gpio5";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



		gcc: qcom,gcc@1800000 {

			compatible = "qcom,gcc-msm8916";

			#clock-cells = <1>;

			#reset-cells = <1>;

			reg = <0x1800000 0x80000>;

		};



		blsp1_uart2: serial@78b0000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x78b0000 0x200>;

			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		intc: interrupt-controller@b000000 {

			compatible = "qcom,msm-qgic2";

			interrupt-controller;

			#interrupt-cells = <3>;

			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;

		};



		timer@b020000 {

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			compatible = "arm,armv7-timer-mem";

			reg = <0xb020000 0x1000>;

			clock-frequency = <19200000>;



			frame@b021000 {

				frame-number = <0>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb021000 0x1000>,

				      <0xb022000 0x1000>;

			};



			frame@b023000 {

				frame-number = <1>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb023000 0x1000>;

				status = "disabled";

			};



			frame@b024000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb024000 0x1000>;

				status = "disabled";

			};



			frame@b025000 {

				frame-number = <3>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb025000 0x1000>;

				status = "disabled";

			};



			frame@b026000 {

				frame-number = <4>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb026000 0x1000>;

				status = "disabled";

			};



			frame@b027000 {

				frame-number = <5>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb027000 0x1000>;

				status = "disabled";

			};



			frame@b028000 {

				frame-number = <6>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb028000 0x1000>;

				status = "disabled";

			};

		};

	};

};