Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 57e65ad7 authored by Lee Jones's avatar Lee Jones Committed by Linus Walleij
Browse files

dmaengine: ste_dma40: Remove unnecessary call to d40_phy_cfg() 



The majority of configuration done in d40_phy_config() pertains
to physical channels. Move the call over to runtime config which
has different code paths for physical and logical channels already,
and make it an exclusive physical channel config function as the
name implies, and drop the is_log argument.

Since we moved the call to runtime_config() it only gets called
for device transfers, so encode the small snippet of configuration
pertaining to memcpy channels into the d40_config_memcpy()
function.

Acked-by: default avatarVinod Koul <vinod.koul@intel.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
[rewrote the commit message]
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 9778256b

drivers/dma/ste_dma40.c

+9 −5
Original line number Diff line number Diff line
@@ -2043,6 +2043,14 @@ static int d40_config_memcpy(struct d40_chan *d40c) 
	} else if (dma_has_cap(DMA_MEMCPY, cap) &&

		   dma_has_cap(DMA_SLAVE, cap)) {

		d40c->dma_cfg = dma40_memcpy_conf_phy;



		/* Generate interrrupt at end of transfer or relink. */

		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);



		/* Generate interrupt on error. */

		d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);

		d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);



	} else {

		chan_err(d40c, "No memcpy\n");

		return -EINVAL;
@@ -2496,9 +2504,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan) 
	}



	pm_runtime_get_sync(d40c->base->dev);

	/* Fill in basic CFG register values */

	d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,

		    &d40c->dst_def_cfg, chan_is_logical(d40c));



	d40_set_prio_realtime(d40c);
@@ -2862,8 +2867,7 @@ static int d40_set_runtime_config(struct dma_chan *chan, 
	if (chan_is_logical(d40c))

		d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);

	else

		d40_phy_cfg(cfg, &d40c->src_def_cfg,

			    &d40c->dst_def_cfg, false);

		d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);



	/* These settings will take precedence later */

	d40c->runtime_addr = config_addr;

drivers/dma/ste_dma40_ll.c

+48 −53
Original line number Diff line number Diff line
@@ -50,15 +50,11 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg, 


}



/* Sets up SRC and DST CFG register for both logical and physical channels */

void d40_phy_cfg(struct stedma40_chan_cfg *cfg,

		 u32 *src_cfg, u32 *dst_cfg, bool is_log)

void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)

{

	u32 src = 0;

	u32 dst = 0;



	if (!is_log) {

		/* Physical channel */

	if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||

	    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {

		/* Set master port to 1 */
@@ -107,7 +103,6 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, 
		src |= 1 << D40_SREG_CFG_PRI_POS;

		dst |= 1 << D40_SREG_CFG_PRI_POS;

	}

	}



	if (cfg->src_info.big_endian)

		src |= 1 << D40_SREG_CFG_LBE_POS;

drivers/dma/ste_dma40_ll.h

+1 −2
Original line number Diff line number Diff line
@@ -432,8 +432,7 @@ enum d40_lli_flags { 


void d40_phy_cfg(struct stedma40_chan_cfg *cfg,

		 u32 *src_cfg,

		 u32 *dst_cfg,

		 bool is_log);

		 u32 *dst_cfg);



void d40_log_cfg(struct stedma40_chan_cfg *cfg,

		 u32 *lcsp1,