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Commit 57b317f9 authored by Kisoo Yu's avatar Kisoo Yu Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll 



The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250.
The clock options are a fixed divided by 2 clock and the output of the
PLL itself. Add support for these new clock instances.

Signed-off-by: default avatarKisoo Yu <ksoo.yu@samsung.com>
Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
[kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c]
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent f10590c9

arch/arm/mach-exynos/clock-exynos5.c

+44 −2
Original line number Diff line number Diff line
@@ -165,11 +165,29 @@ static struct clksrc_clk exynos5_clk_sclk_apll = { 
	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },

};



static struct clksrc_clk exynos5_clk_mout_bpll_fout = {

	.clk	= {

		.name		= "mout_bpll_fout",

	},

	.sources = &clk_src_bpll_fout,

	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },

};



static struct clk *exynos5_clk_src_bpll_list[] = {

	[0] = &clk_fin_bpll,

	[1] = &exynos5_clk_mout_bpll_fout.clk,

};



static struct clksrc_sources exynos5_clk_src_bpll = {

	.sources	= exynos5_clk_src_bpll_list,

	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_bpll_list),

};



static struct clksrc_clk exynos5_clk_mout_bpll = {

	.clk	= {

		.name		= "mout_bpll",

	},

	.sources = &clk_src_bpll,

	.sources = &exynos5_clk_src_bpll,

	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },

};
@@ -207,11 +225,29 @@ static struct clksrc_clk exynos5_clk_mout_epll = { 
	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },

};



static struct clksrc_clk exynos5_clk_mout_mpll_fout = {

	.clk	= {

		.name		= "mout_mpll_fout",

	},

	.sources = &clk_src_mpll_fout,

	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },

};



static struct clk *exynos5_clk_src_mpll_list[] = {

	[0] = &clk_fin_mpll,

	[1] = &exynos5_clk_mout_mpll_fout.clk,

};



static struct clksrc_sources exynos5_clk_src_mpll = {

	.sources	= exynos5_clk_src_mpll_list,

	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_list),

};



struct clksrc_clk exynos5_clk_mout_mpll = {

	.clk = {

		.name		= "mout_mpll",

	},

	.sources = &clk_src_mpll,

	.sources = &exynos5_clk_src_mpll,

	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },

};
@@ -1036,10 +1072,12 @@ static struct clksrc_clk *exynos5_sysclks[] = { 
	&exynos5_clk_mout_apll,

	&exynos5_clk_sclk_apll,

	&exynos5_clk_mout_bpll,

	&exynos5_clk_mout_bpll_fout,

	&exynos5_clk_mout_bpll_user,

	&exynos5_clk_mout_cpll,

	&exynos5_clk_mout_epll,

	&exynos5_clk_mout_mpll,

	&exynos5_clk_mout_mpll_fout,

	&exynos5_clk_mout_mpll_user,

	&exynos5_clk_vpllsrc,

	&exynos5_clk_sclk_vpll,
@@ -1103,7 +1141,9 @@ static struct clk *exynos5_clks[] __initdata = { 
	&exynos5_clk_sclk_hdmi27m,

	&exynos5_clk_sclk_hdmiphy,

	&clk_fout_bpll,

	&clk_fout_bpll_div2,

	&clk_fout_cpll,

	&clk_fout_mpll_div2,

	&exynos5_clk_armclk,

};
@@ -1268,8 +1308,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void) 


	clk_fout_apll.ops = &exynos5_fout_apll_ops;

	clk_fout_bpll.rate = bpll;

	clk_fout_bpll_div2.rate = bpll >> 1;

	clk_fout_cpll.rate = cpll;

	clk_fout_mpll.rate = mpll;

	clk_fout_mpll_div2.rate = mpll >> 1;

	clk_fout_epll.rate = epll;

	clk_fout_vpll.rate = vpll;

arch/arm/mach-exynos/include/mach/regs-clock.h

+2 −0
Original line number Diff line number Diff line
@@ -322,6 +322,8 @@ 
#define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)

#define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)



#define EXYNOS5_PLL_DIV2_SEL			EXYNOS_CLKREG(0x20A24)



#define EXYNOS5_EPLL_LOCK			EXYNOS_CLKREG(0x10030)



#define EXYNOS5_EPLLCON0_LOCKED_SHIFT		(29)

arch/arm/plat-samsung/include/plat/s5p-clock.h

+4 −0
Original line number Diff line number Diff line
@@ -32,8 +32,10 @@ extern struct clk clk_48m; 
extern struct clk s5p_clk_27m;

extern struct clk clk_fout_apll;

extern struct clk clk_fout_bpll;

extern struct clk clk_fout_bpll_div2;

extern struct clk clk_fout_cpll;

extern struct clk clk_fout_mpll;

extern struct clk clk_fout_mpll_div2;

extern struct clk clk_fout_epll;

extern struct clk clk_fout_dpll;

extern struct clk clk_fout_vpll;
@@ -42,8 +44,10 @@ extern struct clk clk_vpll; 


extern struct clksrc_sources clk_src_apll;

extern struct clksrc_sources clk_src_bpll;

extern struct clksrc_sources clk_src_bpll_fout;

extern struct clksrc_sources clk_src_cpll;

extern struct clksrc_sources clk_src_mpll;

extern struct clksrc_sources clk_src_mpll_fout;

extern struct clksrc_sources clk_src_epll;

extern struct clksrc_sources clk_src_dpll;

arch/arm/plat-samsung/s5p-clock.c

+30 −0
Original line number Diff line number Diff line
@@ -67,6 +67,11 @@ struct clk clk_fout_bpll = { 
	.id		= -1,

};



struct clk clk_fout_bpll_div2 = {

	.name		= "fout_bpll_div2",

	.id		= -1,

};



/* CPLL clock output */



struct clk clk_fout_cpll = {
@@ -82,6 +87,11 @@ struct clk clk_fout_mpll = { 
	.id		= -1,

};



struct clk clk_fout_mpll_div2 = {

	.name		= "fout_mpll_div2",

	.id		= -1,

};



/* EPLL clock output */

struct clk clk_fout_epll = {

	.name		= "fout_epll",
@@ -125,6 +135,16 @@ struct clksrc_sources clk_src_bpll = { 
	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),

};



static struct clk *clk_src_bpll_fout_list[] = {

	[0] = &clk_fout_bpll_div2,

	[1] = &clk_fout_bpll,

};



struct clksrc_sources clk_src_bpll_fout = {

	.sources	= clk_src_bpll_fout_list,

	.nr_sources	= ARRAY_SIZE(clk_src_bpll_fout_list),

};



/* Possible clock sources for CPLL Mux */

static struct clk *clk_src_cpll_list[] = {

	[0] = &clk_fin_cpll,
@@ -147,6 +167,16 @@ struct clksrc_sources clk_src_mpll = { 
	.nr_sources	= ARRAY_SIZE(clk_src_mpll_list),

};



static struct clk *clk_src_mpll_fout_list[] = {

	[0] = &clk_fout_mpll_div2,

	[1] = &clk_fout_mpll,

};



struct clksrc_sources clk_src_mpll_fout = {

	.sources	= clk_src_mpll_fout_list,

	.nr_sources	= ARRAY_SIZE(clk_src_mpll_fout_list),

};



/* Possible clock sources for EPLL Mux */

static struct clk *clk_src_epll_list[] = {

	[0] = &clk_fin_epll,