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Commit 56523eef authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'samsung-fixes-2' of... 

Merge tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes

Merge "Samsung 2nd fixes for v4.1" from Kukjin Kim:

- fix second S2R on exynos4412 based Trats2, Odroid U3 boards which
  happened after enabling L2$ and caused by commit 13cfa6c4 ("ARM:
  EXYNOS: Fix CPU idle clock down after CPU off")
  And replace the soc_is_exynosxxx() macro with of_compatible_xxx

- fix dereference of ERR_PTR of of_genpd_get_from_provider()

- fix suspend problem on old DT machines to skip the initialization
  suspend and caused by commit 8b283c02 ("ARM: exynos4/5: convert
  pmu wakeup to stacked domains")

- add keep-power-in-suspend for Peach Boards to support S2R and has
  been missed in previous pull-request for fixes

* tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Use of_machine_is_compatible instead of soc_is_exynos4
  ARM: EXYNOS: Fix failed second suspend on Exynos4
  ARM: EXYNOS: Fix dereference of ERR_PTR returned by of_genpd_get_from_provider
  ARM: EXYNOS: Don't try to initialize suspend on old DT
  ARM: dts: Add keep-power-in-suspend to WiFi SDIO node for Peach Boards
parents cc1c1b5d c1f0ecff

arch/arm/boot/dts/exynos5420-peach-pit.dts

+1 −0
Original line number Diff line number Diff line
@@ -711,6 +711,7 @@ 
	num-slots = <1>;

	broken-cd;

	cap-sdio-irq;

	keep-power-in-suspend;

	card-detect-delay = <200>;

	clock-frequency = <400000000>;

	samsung,dw-mshc-ciu-div = <1>;

arch/arm/boot/dts/exynos5800-peach-pi.dts

+1 −0
Original line number Diff line number Diff line
@@ -674,6 +674,7 @@ 
	num-slots = <1>;

	broken-cd;

	cap-sdio-irq;

	keep-power-in-suspend;

	card-detect-delay = <200>;

	clock-frequency = <400000000>;

	samsung,dw-mshc-ciu-div = <1>;

arch/arm/mach-exynos/common.h

+2 −0
Original line number Diff line number Diff line
@@ -159,6 +159,8 @@ extern void exynos_enter_aftr(void); 


extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;



extern void exynos_set_delayed_reset_assertion(bool enable);



extern void s5p_init_cpu(void __iomem *cpuid_addr);

extern unsigned int samsung_rev(void);

extern void __iomem *cpu_boot_reg_base(void);

arch/arm/mach-exynos/exynos.c

+27 −0
Original line number Diff line number Diff line
@@ -166,6 +166,33 @@ static void __init exynos_init_io(void) 
	exynos_map_io();

}



/*

 * Set or clear the USE_DELAYED_RESET_ASSERTION option. Used by smp code

 * and suspend.

 *

 * This is necessary only on Exynos4 SoCs. When system is running

 * USE_DELAYED_RESET_ASSERTION should be set so the ARM CLK clock down

 * feature could properly detect global idle state when secondary CPU is

 * powered down.

 *

 * However this should not be set when such system is going into suspend.

 */

void exynos_set_delayed_reset_assertion(bool enable)

{

	if (of_machine_is_compatible("samsung,exynos4")) {

		unsigned int tmp, core_id;



		for (core_id = 0; core_id < num_possible_cpus(); core_id++) {

			tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));

			if (enable)

				tmp |= S5P_USE_DELAYED_RESET_ASSERTION;

			else

				tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);

			pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));

		}

	}

}



/*

 * Apparently, these SoCs are not able to wake-up from suspend using

 * the PMU. Too bad. Should they suddenly become capable of such a

arch/arm/mach-exynos/platsmp.c

+2 −37
Original line number Diff line number Diff line
@@ -34,30 +34,6 @@ 


extern void exynos4_secondary_startup(void);



/*

 * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs

 * during hot-(un)plugging CPUx.

 *

 * The feature can be cleared safely during first boot of secondary CPU.

 *

 * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering

 * down a CPU so the CPU idle clock down feature could properly detect global

 * idle state when CPUx is off.

 */

static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable)

{

	if (soc_is_exynos4()) {

		unsigned int tmp;



		tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));

		if (enable)

			tmp |= S5P_USE_DELAYED_RESET_ASSERTION;

		else

			tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);

		pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));

	}

}



#ifdef CONFIG_HOTPLUG_CPU

static inline void cpu_leave_lowpower(u32 core_id)

{
@@ -73,8 +49,6 @@ static inline void cpu_leave_lowpower(u32 core_id) 
	  : "=&r" (v)

	  : "Ir" (CR_C), "Ir" (0x40)

	  : "cc");



	 exynos_set_delayed_reset_assertion(core_id, false);

}



static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
@@ -87,14 +61,6 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) 
		/* Turn the CPU off on next WFI instruction. */

		exynos_cpu_power_down(core_id);



		/*

		 * Exynos4 SoCs require setting

		 * USE_DELAYED_RESET_ASSERTION so the CPU idle

		 * clock down feature could properly detect

		 * global idle state when CPUx is off.

		 */

		exynos_set_delayed_reset_assertion(core_id, true);



		wfi();



		if (pen_release == core_id) {
@@ -371,9 +337,6 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) 
		udelay(10);

	}



	/* No harm if this is called during first boot of secondary CPU */

	exynos_set_delayed_reset_assertion(core_id, false);



	/*

	 * now the secondary core is starting up let it run its

	 * calibrations, then wait for it to finish
@@ -420,6 +383,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) 


	exynos_sysram_init();



	exynos_set_delayed_reset_assertion(true);



	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)

		scu_enable(scu_base_addr());