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Commit 55dc2621 authored by Jilai Wang's avatar Jilai Wang
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ARM: dts: msm: Add NPU_DSP stream IDs for npu

In order to allow NPU Q6 to access IOMMU mapped address, NPU_DSP
stream IDs need to be added.

Change-Id: I63138024c4a602c0c89e086eae2e8bebccb6f050
parent 998fe64d
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+2 −1
Original line number Diff line number Diff line
@@ -15,7 +15,8 @@
		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
					"general_irq";
		iommus = <&apps_smmu 0x1081 0x400>, <&apps_smmu 0x1082 0x400>,
			<&apps_smmu 0x10A1 0x400>, <&apps_smmu 0x10A2 0x400>;
			<&apps_smmu 0x10A1 0x400>, <&apps_smmu 0x10A2 0x400>,
			<&apps_smmu 0x10C1 0x400>, <&apps_smmu 0x10C2 0x400>;

		clocks = <&clock_npucc NPU_CC_XO_CLK>,
				<&clock_npucc NPU_CC_CORE_CLK>,
+2 −1
Original line number Diff line number Diff line
@@ -16,7 +16,8 @@
				<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
					"general_irq";
		iommus = <&apps_smmu 0x1861 0x400>, <&apps_smmu 0x1862 0x400>;
		iommus = <&apps_smmu 0x1861 0x400>, <&apps_smmu 0x1862 0x400>,
			<&apps_smmu 0x1881 0x400>, <&apps_smmu 0x1882 0x400>;

		clocks = <&npucc NPU_CC_XO_CLK>,
				<&npucc NPU_CC_CORE_CLK>,