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Commit 550ab390 authored by Beniamino Galvani's avatar Beniamino Galvani Committed by Carlo Caione
Browse files

ARM: meson: DTS: enable L2 cache 



This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: default avatarBeniamino Galvani <b.galvani@gmail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarCarlo Caione <carlo@caione.org>
parent aeff05a3

arch/arm/boot/dts/meson.dtsi

+7 −0
Original line number Original line Diff line number Diff line
@@ -50,6 +50,13 @@ 
/ {

/ {

	interrupt-parent = <&gic>;

	interrupt-parent = <&gic>;





	L2: l2-cache-controller@c4200000 {

		compatible = "arm,pl310-cache";

		reg = <0xc4200000 0x1000>;

		cache-unified;

		cache-level = <2>;

	};



	gic: interrupt-controller@c4301000 {

	gic: interrupt-controller@c4301000 {

		compatible = "arm,cortex-a9-gic";

		compatible = "arm,cortex-a9-gic";

		reg = <0xc4301000 0x1000>,

		reg = <0xc4301000 0x1000>,

arch/arm/boot/dts/meson6.dtsi

+2 −0
Original line number Original line Diff line number Diff line
@@ -60,12 +60,14 @@ 
		cpu@200 {

		cpu@200 {

			device_type = "cpu";

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x200>;

			reg = <0x200>;

		};

		};





		cpu@201 {

		cpu@201 {

			device_type = "cpu";

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x201>;

			reg = <0x201>;

		};

		};

	};

	};

arch/arm/boot/dts/meson8.dtsi

+4 −0
Original line number Original line Diff line number Diff line
@@ -58,24 +58,28 @@ 
		cpu@200 {

		cpu@200 {

			device_type = "cpu";

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x200>;

			reg = <0x200>;

		};

		};





		cpu@201 {

		cpu@201 {

			device_type = "cpu";

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x201>;

			reg = <0x201>;

		};

		};





		cpu@202 {

		cpu@202 {

			device_type = "cpu";

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x202>;

			reg = <0x202>;

		};

		};





		cpu@203 {

		cpu@203 {

			device_type = "cpu";

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0x203>;

			reg = <0x203>;

		};

		};

	};

	};