Commit 54eff226 authored Sep 19, 2017 by Michał Mirosław Committed by Thierry Reding Nov 01, 2017

clk: tegra: Fix cclk_lp divisor register



According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0e ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent d80a32fe

drivers/clk/tegra/clk-tegra30.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -965,7 +965,7 @@ static void __init tegra30_super_clk_init(void)
		* U71 divider of cclk_lp.
		*/
		clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
		clk_base + SUPER_CCLKG_DIVIDER, 0,
		clk_base + SUPER_CCLKLP_DIVIDER, 0,
		TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
		clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);