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Commit 53ff2641 authored by Lionel Landwerlin's avatar Lionel Landwerlin Committed by Paulo Zanoni
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drm/i915/cnl: only divide up base frequency with crystal source 



We apply this logic to Gen9 as well. We didn't notice this issue as
most part we've encountered so far only use the crystal as source for
their timestamp registers.

Fixes: dab91783 ("drm/i915: expose command stream timestamp frequency to userspace")
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171113233455.12085-5-lionel.g.landwerlin@intel.com
parent 006c2332

drivers/gpu/drm/i915/intel_device_info.c

+8 −8
Original line number Original line Diff line number Diff line
@@ -403,15 +403,15 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) 
				freq = f24_mhz;

				freq = f24_mhz;

				break;

				break;

			}

			}

		}





		/* Now figure out how the command stream's timestamp register

			/* Now figure out how the command stream's timestamp

		 * increments from this frequency (it might increment only

			 * register increments from this frequency (it might

		 * every few clock cycle).

			 * increment only every few clock cycle).

			 */

			 */

			freq >>= 3 - ((rpm_config_reg &

			freq >>= 3 - ((rpm_config_reg &

				       GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>

				       GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>

				      GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);

				      GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);

		}





		return freq;

		return freq;

	}

	}