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Commit 53ecdaa9 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: camera: cpas: Add cpas support for camera v170_130 platform"

parents a5e7a3b0 a1361820

drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c

+8 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include "cpastop_v175_100.h"

#include "cpastop_v175_101.h"

#include "cpastop_v175_120.h"

#include "cpastop_v175_130.h"

#include "cpastop_v480_100.h"



struct cam_camnoc_info *camnoc_info;
@@ -104,6 +105,10 @@ static int cam_cpastop_get_hw_info(struct cam_hw_info *cpas_hw, 
			(hw_caps->cpas_version.minor == 2) &&

			(hw_caps->cpas_version.incr == 0))

			soc_info->hw_version = CAM_CPAS_TITAN_175_V120;

		else if ((hw_caps->cpas_version.major == 1) &&

			(hw_caps->cpas_version.minor == 3) &&

			(hw_caps->cpas_version.incr == 0))

			soc_info->hw_version = CAM_CPAS_TITAN_175_V130;

	} else if ((hw_caps->camera_version.major == 1) &&

		(hw_caps->camera_version.minor == 5) &&

		(hw_caps->camera_version.incr == 0)) {
@@ -591,6 +596,9 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, 
	case CAM_CPAS_TITAN_175_V120:

		camnoc_info = &cam175_cpas120_camnoc_info;

		break;

	case CAM_CPAS_TITAN_175_V130:

		camnoc_info = &cam175_cpas130_camnoc_info;

		break;

	case CAM_CPAS_TITAN_150_V100:

		camnoc_info = &cam150_cpas100_camnoc_info;

		break;

drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v175_130.h

0 → 100644
+760 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/media/platform/msm/camera/cam_cpas/include/cam_cpas_api.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ enum cam_cpas_hw_version { 
	CAM_CPAS_TITAN_175_V100 = 0x175100,

	CAM_CPAS_TITAN_175_V101 = 0x175101,

	CAM_CPAS_TITAN_175_V120 = 0x175120,

	CAM_CPAS_TITAN_175_V130 = 0x175130,

	CAM_CPAS_TITAN_480_V100 = 0x480100,

	CAM_CPAS_TITAN_MAX

};

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c

+5 −2
Original line number Diff line number Diff line
@@ -1232,7 +1232,8 @@ static int cam_vfe_bus_start_wm( 
				ubwc_regs->mode_cfg_0);

		} else if ((camera_hw_version == CAM_CPAS_TITAN_175_V100) ||

			(camera_hw_version == CAM_CPAS_TITAN_175_V101) ||

			(camera_hw_version == CAM_CPAS_TITAN_175_V120)) {

			(camera_hw_version == CAM_CPAS_TITAN_175_V120) ||

			(camera_hw_version == CAM_CPAS_TITAN_175_V130)) {

			struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client

				*ubwc_regs;
@@ -2555,7 +2556,7 @@ static void cam_vfe_bus_update_ubwc_meta_addr( 
		CAM_ERR(CAM_ISP, "Failed to get HW version rc: %d", rc);

		goto end;

	} else if ((camera_hw_version < CAM_CPAS_TITAN_170_V100) ||

		(camera_hw_version > CAM_CPAS_TITAN_175_V120)) {

		(camera_hw_version > CAM_CPAS_TITAN_175_V130)) {

		CAM_ERR(CAM_ISP, "Invalid HW version: %d",

			camera_hw_version);

		goto end;
@@ -2574,6 +2575,7 @@ static void cam_vfe_bus_update_ubwc_meta_addr( 
	case CAM_CPAS_TITAN_175_V100:

	case CAM_CPAS_TITAN_175_V101:

	case CAM_CPAS_TITAN_175_V120:

	case CAM_CPAS_TITAN_175_V130:

		ubwc_3_regs =

			(struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client *)

			regs;
@@ -2787,6 +2789,7 @@ static int cam_vfe_bus_update_ubwc_regs( 
	case CAM_CPAS_TITAN_175_V100:

	case CAM_CPAS_TITAN_175_V101:

	case CAM_CPAS_TITAN_175_V120:

	case CAM_CPAS_TITAN_175_V130:

		rc = cam_vfe_bus_update_ubwc_3_regs(

			wm_data, reg_val_pair, i, j);

		break;

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c

+2 −1
Original line number Diff line number Diff line
@@ -552,7 +552,8 @@ static int cam_vfe_camif_reg_dump_bh( 
	}



	soc_private = camif_priv->soc_info->soc_private;

	if (soc_private->cpas_version == CAM_CPAS_TITAN_175_V120) {

	if (soc_private->cpas_version == CAM_CPAS_TITAN_175_V120 ||

		soc_private->cpas_version == CAM_CPAS_TITAN_175_V130) {

		cam_cpas_reg_read(soc_private->cpas_handle,

			CAM_CPAS_REG_CAMNOC, 0x3A20, true, &val);

		CAM_DBG(CAM_ISP, "IFE0_nRDI_MAXWR_LOW offset 0x3A20 val 0x%x",