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Commit 53d56f79 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'qed-next' 



Manish Chopra says:

====================
qed/qede: Enhancements

This patch series adds these below features support in qed/qede

1) Ntuple filter configuration [via ethtool -n/N]
2) EEE (energy efficient ethernet) support [ethtool --set-eee/show-eee]
3) Coalescing configuration support for VFs [via ethtool -c/C]

Please consider applying this to "net-next"

V1->V2:
* Fixes below Kbuild test robot warning.

drivers/net//ethernet/qlogic/qed/qed_l2.c:
In function 'qed_get_queue_coalesce':
drivers/net//ethernet/qlogic/qed/qed_l2.c:2137:8: error:
implicit declaration of function 'qed_vf_pf_get_coalesce'
[-Werror=implicit-function-declaration]
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents e27a8792 41822878

drivers/net/ethernet/qlogic/qed/qed_dev.c

+117 −28
Original line number Diff line number Diff line
@@ -1684,6 +1684,8 @@ int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params) 
			   "Load request was sent. Load code: 0x%x\n",

			   load_code);



		qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);



		qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);



		p_hwfn->first_on_engine = (load_code ==
@@ -2472,6 +2474,7 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 
{

	u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;

	u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;

	struct qed_mcp_link_capabilities *p_caps;

	struct qed_mcp_link_params *link;



	/* Read global nvm_cfg address */
@@ -2534,6 +2537,7 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 


	/* Read default link configuration */

	link = &p_hwfn->mcp_info->link_input;

	p_caps = &p_hwfn->mcp_info->link_capabilities;

	port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +

			offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);

	link_temp = qed_rd(p_hwfn, p_ptt,
@@ -2588,10 +2592,45 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 
				   NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);

	link->loopback_mode = 0;



	DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,

		   "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",

		   link->speed.forced_speed, link->speed.advertised_speeds,

		   link->speed.autoneg, link->pause.autoneg);

	if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {

		link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +

				   offsetof(struct nvm_cfg1_port, ext_phy));

		link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;

		link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;

		p_caps->default_eee = QED_MCP_EEE_ENABLED;

		link->eee.enable = true;

		switch (link_temp) {

		case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:

			p_caps->default_eee = QED_MCP_EEE_DISABLED;

			link->eee.enable = false;

			break;

		case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:

			p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;

			break;

		case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:

			p_caps->eee_lpi_timer =

			    EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;

			break;

		case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:

			p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;

			break;

		}



		link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;

		link->eee.tx_lpi_enable = link->eee.enable;

		link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;

	} else {

		p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;

	}



	DP_VERBOSE(p_hwfn,

		   NETIF_MSG_LINK,

		   "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",

		   link->speed.forced_speed,

		   link->speed.advertised_speeds,

		   link->speed.autoneg,

		   link->pause.autoneg,

		   p_caps->default_eee, p_caps->eee_lpi_timer);



	/* Read Multi-function information from shmem */

	addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
@@ -2751,6 +2790,27 @@ static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 
		qed_hw_info_port_num_ah(p_hwfn, p_ptt);

}



static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)

{

	struct qed_mcp_link_capabilities *p_caps;

	u32 eee_status;



	p_caps = &p_hwfn->mcp_info->link_capabilities;

	if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)

		return;



	p_caps->eee_speed_caps = 0;

	eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +

			    offsetof(struct public_port, eee_status));

	eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>

			EEE_SUPPORTED_SPEED_OFFSET;



	if (eee_status & EEE_1G_SUPPORTED)

		p_caps->eee_speed_caps |= QED_EEE_1G_ADV;

	if (eee_status & EEE_10G_ADV)

		p_caps->eee_speed_caps |= QED_EEE_10G_ADV;

}



static int

qed_get_hw_info(struct qed_hwfn *p_hwfn,

		struct qed_ptt *p_ptt,
@@ -2767,6 +2827,8 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn, 


	qed_hw_info_port_num(p_hwfn, p_ptt);



	qed_mcp_get_capabilities(p_hwfn, p_ptt);



	qed_hw_get_nvm_info(p_hwfn, p_ptt);



	rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
@@ -2785,6 +2847,8 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn, 
				p_hwfn->mcp_info->func_info.ovlan;



		qed_mcp_cmd_port_init(p_hwfn, p_ptt);



		qed_get_eee_caps(p_hwfn, p_ptt);

	}



	if (qed_mcp_is_init(p_hwfn)) {
@@ -3630,7 +3694,7 @@ static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 
	}



	p_coal_timeset = p_eth_qzone;

	memset(p_coal_timeset, 0, eth_qzone_size);

	memset(p_eth_qzone, 0, eth_qzone_size);

	SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);

	SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);

	qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
@@ -3638,12 +3702,46 @@ static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 
	return 0;

}



int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,

			 u16 coalesce, u16 qid, u16 sb_id)

int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)

{

	struct qed_queue_cid *p_cid = p_handle;

	struct qed_hwfn *p_hwfn;

	struct qed_ptt *p_ptt;

	int rc = 0;



	p_hwfn = p_cid->p_owner;



	if (IS_VF(p_hwfn->cdev))

		return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);



	p_ptt = qed_ptt_acquire(p_hwfn);

	if (!p_ptt)

		return -EAGAIN;



	if (rx_coal) {

		rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);

		if (rc)

			goto out;

		p_hwfn->cdev->rx_coalesce_usecs = rx_coal;

	}



	if (tx_coal) {

		rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);

		if (rc)

			goto out;

		p_hwfn->cdev->tx_coalesce_usecs = tx_coal;

	}

out:

	qed_ptt_release(p_hwfn, p_ptt);

	return rc;

}



int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,

			 struct qed_ptt *p_ptt,

			 u16 coalesce, struct qed_queue_cid *p_cid)

{

	struct ustorm_eth_queue_zone eth_qzone;

	u8 timeset, timer_res;

	u16 fw_qid = 0;

	u32 address;

	int rc;
@@ -3660,32 +3758,29 @@ int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 
	}

	timeset = (u8)(coalesce >> timer_res);



	rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid);

	if (rc)

		return rc;



	rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);

	rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,

				   p_cid->sb_igu_id, false);

	if (rc)

		goto out;



	address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);

	address = BAR0_MAP_REG_USDM_RAM +

		  USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);



	rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,

			      sizeof(struct ustorm_eth_queue_zone), timeset);

	if (rc)

		goto out;



	p_hwfn->cdev->rx_coalesce_usecs = coalesce;

out:

	return rc;

}



int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,

			 u16 coalesce, u16 qid, u16 sb_id)

int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,

			 struct qed_ptt *p_ptt,

			 u16 coalesce, struct qed_queue_cid *p_cid)

{

	struct xstorm_eth_queue_zone eth_qzone;

	u8 timeset, timer_res;

	u16 fw_qid = 0;

	u32 address;

	int rc;
@@ -3702,22 +3797,16 @@ int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 
	}

	timeset = (u8)(coalesce >> timer_res);



	rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid);

	if (rc)

		return rc;



	rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);

	rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,

				   p_cid->sb_igu_id, true);

	if (rc)

		goto out;



	address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);

	address = BAR0_MAP_REG_XSDM_RAM +

		  XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);



	rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,

			      sizeof(struct xstorm_eth_queue_zone), timeset);

	if (rc)

		goto out;



	p_hwfn->cdev->tx_coalesce_usecs = coalesce;

out:

	return rc;

}

drivers/net/ethernet/qlogic/qed/qed_dev_api.h

+20 −23
Original line number Diff line number Diff line
@@ -443,38 +443,35 @@ int qed_final_cleanup(struct qed_hwfn *p_hwfn, 
		      struct qed_ptt *p_ptt, u16 id, bool is_vf);



/**

 * @brief qed_set_rxq_coalesce - Configure coalesce parameters for an Rx queue

 * The fact that we can configure coalescing to up to 511, but on varying

 * accuracy [the bigger the value the less accurate] up to a mistake of 3usec

 * for the highest values.

 * @brief qed_get_queue_coalesce - Retrieve coalesce value for a given queue.

 *

 * @param p_hwfn

 * @param p_ptt

 * @param coalesce - Coalesce value in micro seconds.

 * @param qid - Queue index.

 * @param qid - SB Id

 * @param p_coal - store coalesce value read from the hardware.

 * @param p_handle

 *

 * @return int

 */

int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,

			 u16 coalesce, u16 qid, u16 sb_id);

 **/

int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *coal, void *handle);



/**

 * @brief qed_set_txq_coalesce - Configure coalesce parameters for a Tx queue

 * While the API allows setting coalescing per-qid, all tx queues sharing a

 * SB should be in same range [i.e., either 0-0x7f, 0x80-0xff or 0x100-0x1ff]

 * @brief qed_set_queue_coalesce - Configure coalesce parameters for Rx and

 *    Tx queue. The fact that we can configure coalescing to up to 511, but on

 *    varying accuracy [the bigger the value the less accurate] up to a mistake

 *    of 3usec for the highest values.

 *    While the API allows setting coalescing per-qid, all queues sharing a SB

 *    should be in same range [i.e., either 0-0x7f, 0x80-0xff or 0x100-0x1ff]

 *    otherwise configuration would break.

 *

 * @param p_hwfn

 * @param p_ptt

 * @param coalesce - Coalesce value in micro seconds.

 * @param qid - Queue index.

 * @param qid - SB Id

 *

 * @param rx_coal - Rx Coalesce value in micro seconds.

 * @param tx_coal - TX Coalesce value in micro seconds.

 * @param p_handle

 *

 * @return int

 */

int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,

			 u16 coalesce, u16 qid, u16 sb_id);

 **/

int

qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle);





const char *qed_hw_get_resc_name(enum qed_resources res_id);

#endif

drivers/net/ethernet/qlogic/qed/qed_hsi.h

+49 −0
Original line number Diff line number Diff line
@@ -10825,6 +10825,17 @@ struct eth_phy_cfg { 
#define ETH_LOOPBACK_EXT		(3)

#define ETH_LOOPBACK_MAC		(4)



	u32 eee_cfg;

#define EEE_CFG_EEE_ENABLED			BIT(0)

#define EEE_CFG_TX_LPI				BIT(1)

#define EEE_CFG_ADV_SPEED_1G			BIT(2)

#define EEE_CFG_ADV_SPEED_10G			BIT(3)

#define EEE_TX_TIMER_USEC_MASK			(0xfffffff0)

#define EEE_TX_TIMER_USEC_OFFSET		4

#define EEE_TX_TIMER_USEC_BALANCED_TIME		(0xa00)

#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME	(0x100)

#define EEE_TX_TIMER_USEC_LATENCY_TIME		(0x6000)



	u32 feature_config_flags;

#define ETH_EEE_MODE_ADV_LPI		(1 << 0)

};
@@ -11242,6 +11253,25 @@ struct public_port { 
	u32 wol_pkt_len;

	u32 wol_pkt_details;

	struct dcb_dscp_map dcb_dscp_map;



	u32 eee_status;

#define EEE_ACTIVE_BIT			BIT(0)

#define EEE_LD_ADV_STATUS_MASK		0x000000f0

#define EEE_LD_ADV_STATUS_OFFSET	4

#define EEE_1G_ADV			BIT(1)

#define EEE_10G_ADV			BIT(2)

#define EEE_LP_ADV_STATUS_MASK		0x00000f00

#define EEE_LP_ADV_STATUS_OFFSET	8

#define EEE_SUPPORTED_SPEED_MASK	0x0000f000

#define EEE_SUPPORTED_SPEED_OFFSET	12

#define EEE_1G_SUPPORTED		BIT(1)

#define EEE_10G_SUPPORTED		BIT(2)



	u32 eee_remote;

#define EEE_REMOTE_TW_TX_MASK   0x0000ffff

#define EEE_REMOTE_TW_TX_OFFSET 0

#define EEE_REMOTE_TW_RX_MASK   0xffff0000

#define EEE_REMOTE_TW_RX_OFFSET 16

};



struct public_func {
@@ -11570,6 +11600,9 @@ struct public_drv_mb { 
#define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL	0x002b0000

#define DRV_MSG_CODE_OS_WOL			0x002e0000



#define DRV_MSG_CODE_FEATURE_SUPPORT		0x00300000

#define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT	0x00310000



#define DRV_MSG_SEQ_NUMBER_MASK			0x0000ffff



	u32 drv_mb_param;
@@ -11653,6 +11686,10 @@ struct public_drv_mb { 
#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT	8

#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK		0x0000FF00



#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK		0x0000FFFF

#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET	0

#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE		0x00000002



	u32 fw_mb_header;

#define FW_MSG_CODE_MASK			0xffff0000

#define FW_MSG_CODE_UNSUPPORTED                 0x00000000
@@ -11696,6 +11733,9 @@ struct public_drv_mb { 
#define FW_MB_PARAM_GET_PF_RDMA_IWARP		0x2

#define FW_MB_PARAM_GET_PF_RDMA_BOTH		0x3



/* get MFW feature support response */

#define FW_MB_PARAM_FEATURE_SUPPORT_EEE		0x00000002



#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR	(1 << 0)



	u32 drv_pulse_mb;
@@ -11891,7 +11931,16 @@ struct nvm_cfg1_port { 
#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX			0x4

	u32 phy_cfg;

	u32 mgmt_traffic;



	u32 ext_phy;

	/* EEE power saving mode */

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK		0x00FF0000

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET		16

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED		0x0

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED		0x1

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE		0x2

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY		0x3



	u32 mba_cfg1;

	u32 mba_cfg2;

	u32 vf_cfg;

drivers/net/ethernet/qlogic/qed/qed_l2.c

+115 −0
Original line number Diff line number Diff line
@@ -2047,6 +2047,106 @@ qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 
	return qed_spq_post(p_hwfn, p_ent, NULL);

}



int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn,

			 struct qed_ptt *p_ptt,

			 struct qed_queue_cid *p_cid, u16 *p_rx_coal)

{

	u32 coalesce, address, is_valid;

	struct cau_sb_entry sb_entry;

	u8 timer_res;

	int rc;



	rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +

			       p_cid->sb_igu_id * sizeof(u64),

			       (u64)(uintptr_t)&sb_entry, 2, 0);

	if (rc) {

		DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);

		return rc;

	}



	timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0);



	address = BAR0_MAP_REG_USDM_RAM +

		  USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);

	coalesce = qed_rd(p_hwfn, p_ptt, address);



	is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);

	if (!is_valid)

		return -EINVAL;



	coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);

	*p_rx_coal = (u16)(coalesce << timer_res);



	return 0;

}



int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn,

			 struct qed_ptt *p_ptt,

			 struct qed_queue_cid *p_cid, u16 *p_tx_coal)

{

	u32 coalesce, address, is_valid;

	struct cau_sb_entry sb_entry;

	u8 timer_res;

	int rc;



	rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +

			       p_cid->sb_igu_id * sizeof(u64),

			       (u64)(uintptr_t)&sb_entry, 2, 0);

	if (rc) {

		DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);

		return rc;

	}



	timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1);



	address = BAR0_MAP_REG_XSDM_RAM +

		  XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);

	coalesce = qed_rd(p_hwfn, p_ptt, address);



	is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);

	if (!is_valid)

		return -EINVAL;



	coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);

	*p_tx_coal = (u16)(coalesce << timer_res);



	return 0;

}



int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *p_coal, void *handle)

{

	struct qed_queue_cid *p_cid = handle;

	struct qed_ptt *p_ptt;

	int rc = 0;



	if (IS_VF(p_hwfn->cdev)) {

		rc = qed_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid);

		if (rc)

			DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");



		return rc;

	}



	p_ptt = qed_ptt_acquire(p_hwfn);

	if (!p_ptt)

		return -EAGAIN;



	if (p_cid->b_is_rx) {

		rc = qed_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);

		if (rc)

			goto out;

	} else {

		rc = qed_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);

		if (rc)

			goto out;

	}



out:

	qed_ptt_release(p_hwfn, p_ptt);



	return rc;

}



static int qed_fill_eth_dev_info(struct qed_dev *cdev,

				 struct qed_dev_eth_info *info)

{
@@ -2696,6 +2796,20 @@ static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie, 
	return rc;

}



static int qed_get_coalesce(struct qed_dev *cdev, u16 *coal, void *handle)

{

	struct qed_queue_cid *p_cid = handle;

	struct qed_hwfn *p_hwfn;

	int rc;



	p_hwfn = p_cid->p_owner;

	rc = qed_get_queue_coalesce(p_hwfn, coal, handle);

	if (rc)

		DP_NOTICE(p_hwfn, "Unable to read queue calescing\n");



	return rc;

}



static int qed_fp_cqe_completion(struct qed_dev *dev,

				 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)

{
@@ -2739,6 +2853,7 @@ static const struct qed_eth_ops qed_eth_ops_pass = { 
	.tunn_config = &qed_tunn_configure,

	.ntuple_filter_config = &qed_ntuple_arfs_filter_config,

	.configure_arfs_searcher = &qed_configure_arfs_searcher,

	.get_coalesce = &qed_get_coalesce,

};



const struct qed_eth_ops *qed_get_eth_ops(void)

drivers/net/ethernet/qlogic/qed/qed_l2.h

+17 −1
Original line number Diff line number Diff line
@@ -400,4 +400,20 @@ qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, 


u8 qed_mcast_bin_from_mac(u8 *mac);



#endif /* _QED_L2_H */
 
int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,

			 struct qed_ptt *p_ptt,

			 u16 coalesce, struct qed_queue_cid *p_cid);



int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,

			 struct qed_ptt *p_ptt,

			 u16 coalesce, struct qed_queue_cid *p_cid);



int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn,

			 struct qed_ptt *p_ptt,

			 struct qed_queue_cid *p_cid, u16 *p_hw_coal);



int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn,

			 struct qed_ptt *p_ptt,

			 struct qed_queue_cid *p_cid, u16 *p_hw_coal);



#endif