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Commit 53990e41 authored by Stefan Agner's avatar Stefan Agner Committed by Dave Airlie
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drm: mxsfb: fix pixel clock polarity 



The DRM subsystem specifies the pixel clock polarity from a
controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
the controller drives the data on pixel clocks falling edge.
That is the controllers DOTCLK_POL=0 (Default is data launched
at negative edge).

Also change the data enable logic to be high active by default
and only change if explicitly requested via bus_flags. With
that defaults are:
- Data enable: high active
- Pixel clock polarity: controller drives data on negative edge

Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Acked-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 10f2889b

drivers/gpu/drm/mxsfb/mxsfb_crtc.c

+9 −2
Original line number Diff line number Diff line
@@ -196,9 +196,16 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb) 
		vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;

	if (m->flags & DRM_MODE_FLAG_PVSYNC)

		vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;

	if (bus_flags & DRM_BUS_FLAG_DE_HIGH)

	/* Make sure Data Enable is high active by default */

	if (!(bus_flags & DRM_BUS_FLAG_DE_LOW))

		vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;

	if (bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)

	/*

	 * DRM_BUS_FLAG_PIXDATA_ defines are controller centric,

	 * controllers VDCTRL0_DOTCLK is display centric.

	 * Drive on positive edge       -> display samples on falling edge

	 * DRM_BUS_FLAG_PIXDATA_POSEDGE -> VDCTRL0_DOTCLK_ACT_FALLING

	 */

	if (bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE)

		vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;



	writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0);