Commit 53676174 authored Apr 09, 2020 by Cong Zhang

ARM: align the start and end of v7_setup_stack to cache line



The v7_setup_stack is used when D-cache disabled. When CPU is reading
something nearby with D-cache enabled. It is possible to read
v7_setup_stack to cache line. There is a risk that when cache line write
back the data, v7_setup_stack may already been modified by other CPU with
D-cache disabled. 
The change make v7_setup_stack align cache line size and use the whole 
cache line to prevent corrupting v7_setup_stack.

Change-Id: I13be3c49beafd69d6e86ffd28d5f3ba998aaa8c3
Signed-off-by: Cong Zhang <congzhan@codeaurora.org>

parent a595e17a

arch/arm/mm/proc-v7.S

+3 −2

Original line number	Diff line number	Diff line
		@@ -18,6 +18,7 @@
		#include <asm/pgtable-hwdef.h>
		#include <asm/pgtable.h>
		#include <asm/memory.h>
		#include <asm/cache.h>

		#include "proc-macros.S"

		@@ -548,10 +549,10 @@ __v7_setup_stack_ptr:
		ENDPROC(__v7_setup)

		.bss
		.align 2
		.align L1_CACHE_SHIFT
		__v7_setup_stack:
		.space 4 * 7 @ 7 registers

		.align L1_CACHE_SHIFT
		__INITDATA

		.weak cpu_v7_bugs_init