Loading include/asm-avr32/sysreg.h +249 −294 Original line number Diff line number Diff line Loading @@ -7,8 +7,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __ASM_AVR32_SYSREG_H__ #define __ASM_AVR32_SYSREG_H__ #ifndef __ASM_AVR32_SYSREG_H #define __ASM_AVR32_SYSREG_H /* sysreg register offsets */ #define SYSREG_SR 0x0000 Loading Loading @@ -60,6 +60,9 @@ #define SYSREG_PCNT1 0x0134 #define SYSREG_PCCR 0x0138 #define SYSREG_BEAR 0x013c #define SYSREG_SABAL 0x0300 #define SYSREG_SABAH 0x0304 #define SYSREG_SABD 0x0308 /* Bitfields in SR */ #define SYSREG_SR_C_OFFSET 0 Loading @@ -72,6 +75,12 @@ #define SYSREG_SR_V_SIZE 1 #define SYSREG_Q_OFFSET 4 #define SYSREG_Q_SIZE 1 #define SYSREG_L_OFFSET 5 #define SYSREG_L_SIZE 1 #define SYSREG_T_OFFSET 14 #define SYSREG_T_SIZE 1 #define SYSREG_SR_R_OFFSET 15 #define SYSREG_SR_R_SIZE 1 #define SYSREG_GM_OFFSET 16 #define SYSREG_GM_SIZE 1 #define SYSREG_I0M_OFFSET 17 Loading @@ -96,15 +105,9 @@ #define SYSREG_DM_SIZE 1 #define SYSREG_SR_J_OFFSET 28 #define SYSREG_SR_J_SIZE 1 #define SYSREG_R_OFFSET 29 #define SYSREG_R_SIZE 1 #define SYSREG_H_OFFSET 30 #define SYSREG_H_OFFSET 29 #define SYSREG_H_SIZE 1 /* Bitfields in EVBA */ /* Bitfields in ACBA */ /* Bitfields in CPUCR */ #define SYSREG_BI_OFFSET 0 #define SYSREG_BI_SIZE 1 Loading @@ -119,79 +122,21 @@ #define SYSREG_IEE_OFFSET 5 #define SYSREG_IEE_SIZE 1 /* Bitfields in ECR */ #define SYSREG_ECR_OFFSET 0 #define SYSREG_ECR_SIZE 32 /* Bitfields in RSR_SUP */ /* Bitfields in RSR_INT0 */ /* Bitfields in RSR_INT1 */ /* Bitfields in RSR_INT2 */ /* Bitfields in RSR_INT3 */ /* Bitfields in RSR_EX */ /* Bitfields in RSR_NMI */ /* Bitfields in RSR_DBG */ /* Bitfields in RAR_SUP */ /* Bitfields in RAR_INT0 */ /* Bitfields in RAR_INT1 */ /* Bitfields in RAR_INT2 */ /* Bitfields in RAR_INT3 */ /* Bitfields in RAR_EX */ /* Bitfields in RAR_NMI */ /* Bitfields in RAR_DBG */ /* Bitfields in JECR */ /* Bitfields in JOSP */ /* Bitfields in JAVA_LV0 */ /* Bitfields in JAVA_LV1 */ /* Bitfields in JAVA_LV2 */ /* Bitfields in JAVA_LV3 */ /* Bitfields in JAVA_LV4 */ /* Bitfields in JAVA_LV5 */ /* Bitfields in JAVA_LV6 */ /* Bitfields in JAVA_LV7 */ /* Bitfields in JTBA */ /* Bitfields in JBCR */ /* Bitfields in CONFIG0 */ #define SYSREG_CONFIG0_R_OFFSET 0 #define SYSREG_CONFIG0_R_SIZE 1 #define SYSREG_CONFIG0_D_OFFSET 1 #define SYSREG_CONFIG0_D_SIZE 1 #define SYSREG_CONFIG0_S_OFFSET 2 #define SYSREG_CONFIG0_S_SIZE 1 #define SYSREG_O_OFFSET 3 #define SYSREG_O_SIZE 1 #define SYSREG_P_OFFSET 4 #define SYSREG_P_SIZE 1 #define SYSREG_CONFIG0_O_OFFSET 3 #define SYSREG_CONFIG0_O_SIZE 1 #define SYSREG_CONFIG0_P_OFFSET 4 #define SYSREG_CONFIG0_P_SIZE 1 #define SYSREG_CONFIG0_J_OFFSET 5 #define SYSREG_CONFIG0_J_SIZE 1 #define SYSREG_F_OFFSET 6 #define SYSREG_F_SIZE 1 #define SYSREG_CONFIG0_F_OFFSET 6 #define SYSREG_CONFIG0_F_SIZE 1 #define SYSREG_MMUT_OFFSET 7 #define SYSREG_MMUT_SIZE 3 #define SYSREG_AR_OFFSET 10 Loading @@ -211,7 +156,7 @@ #define SYSREG_DSET_OFFSET 6 #define SYSREG_DSET_SIZE 4 #define SYSREG_IASS_OFFSET 10 #define SYSREG_IASS_SIZE 2 #define SYSREG_IASS_SIZE 3 #define SYSREG_ILSZ_OFFSET 13 #define SYSREG_ILSZ_SIZE 3 #define SYSREG_ISET_OFFSET 16 Loading @@ -221,10 +166,6 @@ #define SYSREG_IMMUSZ_OFFSET 26 #define SYSREG_IMMUSZ_SIZE 6 /* Bitfields in COUNT */ /* Bitfields in COMPARE */ /* Bitfields in TLBEHI */ #define SYSREG_ASID_OFFSET 0 #define SYSREG_ASID_SIZE 8 Loading Loading @@ -253,10 +194,6 @@ #define SYSREG_PFN_OFFSET 10 #define SYSREG_PFN_SIZE 22 /* Bitfields in PTBR */ /* Bitfields in TLBEAR */ /* Bitfields in MMUCR */ #define SYSREG_E_OFFSET 0 #define SYSREG_E_SIZE 1 Loading @@ -277,19 +214,29 @@ #define SYSREG_IRP_OFFSET 26 #define SYSREG_IRP_SIZE 6 /* Bitfields in TLBARLO */ /* Bitfields in TLBARHI */ /* Bitfields in PCCNT */ /* Bitfields in PCNT0 */ /* Bitfields in PCNT1 */ /* Bitfields in PCCR */ /* Bitfields in BEAR */ #define SYSREG_PCCR_R_OFFSET 1 #define SYSREG_PCCR_R_SIZE 1 #define SYSREG_PCCR_C_OFFSET 2 #define SYSREG_PCCR_C_SIZE 1 #define SYSREG_PCCR_S_OFFSET 3 #define SYSREG_PCCR_S_SIZE 1 #define SYSREG_IEC_OFFSET 4 #define SYSREG_IEC_SIZE 1 #define SYSREG_IE0_OFFSET 5 #define SYSREG_IE0_SIZE 1 #define SYSREG_IE1_OFFSET 6 #define SYSREG_IE1_SIZE 1 #define SYSREG_FC_OFFSET 8 #define SYSREG_FC_SIZE 1 #define SYSREG_F0_OFFSET 9 #define SYSREG_F0_SIZE 1 #define SYSREG_F1_OFFSET 10 #define SYSREG_F1_SIZE 1 #define SYSREG_CONF0_OFFSET 12 #define SYSREG_CONF0_SIZE 6 #define SYSREG_CONF1_OFFSET 18 #define SYSREG_CONF1_SIZE 6 /* Constants for ECR */ #define ECR_UNRECOVERABLE 0 Loading @@ -315,18 +262,26 @@ #define ECR_TLB_MISS_W 28 /* Bit manipulation macros */ #define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) #define SYSREG_BF(name,value) (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) << SYSREG_##name##_OFFSET) #define SYSREG_BFEXT(name,value) (((value) >> SYSREG_##name##_OFFSET) & ((1 << SYSREG_##name##_SIZE) - 1)) #define SYSREG_BFINS(name,value,old) (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) << SYSREG_##name##_OFFSET)) | SYSREG_BF(name,value)) #define SYSREG_BIT(name) \ (1 << SYSREG_##name##_OFFSET) #define SYSREG_BF(name,value) \ (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \ << SYSREG_##name##_OFFSET) #define SYSREG_BFEXT(name,value)\ (((value) >> SYSREG_##name##_OFFSET) \ & ((1 << SYSREG_##name##_SIZE) - 1)) #define SYSREG_BFINS(name,value,old) \ (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \ << SYSREG_##name##_OFFSET)) \ | SYSREG_BF(name,value)) /* Register access macros */ #ifdef __CHECKER__ extern unsigned long __builtin_mfsr(unsigned long reg); extern void __builtin_mtsr(unsigned long reg, unsigned long value); #endif /* Register access macros */ #define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg) #define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value) #endif /* __ASM_AVR32_SYSREG_H__ */ #endif /* __ASM_AVR32_SYSREG_H */ Loading
include/asm-avr32/sysreg.h +249 −294 Original line number Diff line number Diff line Loading @@ -7,8 +7,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __ASM_AVR32_SYSREG_H__ #define __ASM_AVR32_SYSREG_H__ #ifndef __ASM_AVR32_SYSREG_H #define __ASM_AVR32_SYSREG_H /* sysreg register offsets */ #define SYSREG_SR 0x0000 Loading Loading @@ -60,6 +60,9 @@ #define SYSREG_PCNT1 0x0134 #define SYSREG_PCCR 0x0138 #define SYSREG_BEAR 0x013c #define SYSREG_SABAL 0x0300 #define SYSREG_SABAH 0x0304 #define SYSREG_SABD 0x0308 /* Bitfields in SR */ #define SYSREG_SR_C_OFFSET 0 Loading @@ -72,6 +75,12 @@ #define SYSREG_SR_V_SIZE 1 #define SYSREG_Q_OFFSET 4 #define SYSREG_Q_SIZE 1 #define SYSREG_L_OFFSET 5 #define SYSREG_L_SIZE 1 #define SYSREG_T_OFFSET 14 #define SYSREG_T_SIZE 1 #define SYSREG_SR_R_OFFSET 15 #define SYSREG_SR_R_SIZE 1 #define SYSREG_GM_OFFSET 16 #define SYSREG_GM_SIZE 1 #define SYSREG_I0M_OFFSET 17 Loading @@ -96,15 +105,9 @@ #define SYSREG_DM_SIZE 1 #define SYSREG_SR_J_OFFSET 28 #define SYSREG_SR_J_SIZE 1 #define SYSREG_R_OFFSET 29 #define SYSREG_R_SIZE 1 #define SYSREG_H_OFFSET 30 #define SYSREG_H_OFFSET 29 #define SYSREG_H_SIZE 1 /* Bitfields in EVBA */ /* Bitfields in ACBA */ /* Bitfields in CPUCR */ #define SYSREG_BI_OFFSET 0 #define SYSREG_BI_SIZE 1 Loading @@ -119,79 +122,21 @@ #define SYSREG_IEE_OFFSET 5 #define SYSREG_IEE_SIZE 1 /* Bitfields in ECR */ #define SYSREG_ECR_OFFSET 0 #define SYSREG_ECR_SIZE 32 /* Bitfields in RSR_SUP */ /* Bitfields in RSR_INT0 */ /* Bitfields in RSR_INT1 */ /* Bitfields in RSR_INT2 */ /* Bitfields in RSR_INT3 */ /* Bitfields in RSR_EX */ /* Bitfields in RSR_NMI */ /* Bitfields in RSR_DBG */ /* Bitfields in RAR_SUP */ /* Bitfields in RAR_INT0 */ /* Bitfields in RAR_INT1 */ /* Bitfields in RAR_INT2 */ /* Bitfields in RAR_INT3 */ /* Bitfields in RAR_EX */ /* Bitfields in RAR_NMI */ /* Bitfields in RAR_DBG */ /* Bitfields in JECR */ /* Bitfields in JOSP */ /* Bitfields in JAVA_LV0 */ /* Bitfields in JAVA_LV1 */ /* Bitfields in JAVA_LV2 */ /* Bitfields in JAVA_LV3 */ /* Bitfields in JAVA_LV4 */ /* Bitfields in JAVA_LV5 */ /* Bitfields in JAVA_LV6 */ /* Bitfields in JAVA_LV7 */ /* Bitfields in JTBA */ /* Bitfields in JBCR */ /* Bitfields in CONFIG0 */ #define SYSREG_CONFIG0_R_OFFSET 0 #define SYSREG_CONFIG0_R_SIZE 1 #define SYSREG_CONFIG0_D_OFFSET 1 #define SYSREG_CONFIG0_D_SIZE 1 #define SYSREG_CONFIG0_S_OFFSET 2 #define SYSREG_CONFIG0_S_SIZE 1 #define SYSREG_O_OFFSET 3 #define SYSREG_O_SIZE 1 #define SYSREG_P_OFFSET 4 #define SYSREG_P_SIZE 1 #define SYSREG_CONFIG0_O_OFFSET 3 #define SYSREG_CONFIG0_O_SIZE 1 #define SYSREG_CONFIG0_P_OFFSET 4 #define SYSREG_CONFIG0_P_SIZE 1 #define SYSREG_CONFIG0_J_OFFSET 5 #define SYSREG_CONFIG0_J_SIZE 1 #define SYSREG_F_OFFSET 6 #define SYSREG_F_SIZE 1 #define SYSREG_CONFIG0_F_OFFSET 6 #define SYSREG_CONFIG0_F_SIZE 1 #define SYSREG_MMUT_OFFSET 7 #define SYSREG_MMUT_SIZE 3 #define SYSREG_AR_OFFSET 10 Loading @@ -211,7 +156,7 @@ #define SYSREG_DSET_OFFSET 6 #define SYSREG_DSET_SIZE 4 #define SYSREG_IASS_OFFSET 10 #define SYSREG_IASS_SIZE 2 #define SYSREG_IASS_SIZE 3 #define SYSREG_ILSZ_OFFSET 13 #define SYSREG_ILSZ_SIZE 3 #define SYSREG_ISET_OFFSET 16 Loading @@ -221,10 +166,6 @@ #define SYSREG_IMMUSZ_OFFSET 26 #define SYSREG_IMMUSZ_SIZE 6 /* Bitfields in COUNT */ /* Bitfields in COMPARE */ /* Bitfields in TLBEHI */ #define SYSREG_ASID_OFFSET 0 #define SYSREG_ASID_SIZE 8 Loading Loading @@ -253,10 +194,6 @@ #define SYSREG_PFN_OFFSET 10 #define SYSREG_PFN_SIZE 22 /* Bitfields in PTBR */ /* Bitfields in TLBEAR */ /* Bitfields in MMUCR */ #define SYSREG_E_OFFSET 0 #define SYSREG_E_SIZE 1 Loading @@ -277,19 +214,29 @@ #define SYSREG_IRP_OFFSET 26 #define SYSREG_IRP_SIZE 6 /* Bitfields in TLBARLO */ /* Bitfields in TLBARHI */ /* Bitfields in PCCNT */ /* Bitfields in PCNT0 */ /* Bitfields in PCNT1 */ /* Bitfields in PCCR */ /* Bitfields in BEAR */ #define SYSREG_PCCR_R_OFFSET 1 #define SYSREG_PCCR_R_SIZE 1 #define SYSREG_PCCR_C_OFFSET 2 #define SYSREG_PCCR_C_SIZE 1 #define SYSREG_PCCR_S_OFFSET 3 #define SYSREG_PCCR_S_SIZE 1 #define SYSREG_IEC_OFFSET 4 #define SYSREG_IEC_SIZE 1 #define SYSREG_IE0_OFFSET 5 #define SYSREG_IE0_SIZE 1 #define SYSREG_IE1_OFFSET 6 #define SYSREG_IE1_SIZE 1 #define SYSREG_FC_OFFSET 8 #define SYSREG_FC_SIZE 1 #define SYSREG_F0_OFFSET 9 #define SYSREG_F0_SIZE 1 #define SYSREG_F1_OFFSET 10 #define SYSREG_F1_SIZE 1 #define SYSREG_CONF0_OFFSET 12 #define SYSREG_CONF0_SIZE 6 #define SYSREG_CONF1_OFFSET 18 #define SYSREG_CONF1_SIZE 6 /* Constants for ECR */ #define ECR_UNRECOVERABLE 0 Loading @@ -315,18 +262,26 @@ #define ECR_TLB_MISS_W 28 /* Bit manipulation macros */ #define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) #define SYSREG_BF(name,value) (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) << SYSREG_##name##_OFFSET) #define SYSREG_BFEXT(name,value) (((value) >> SYSREG_##name##_OFFSET) & ((1 << SYSREG_##name##_SIZE) - 1)) #define SYSREG_BFINS(name,value,old) (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) << SYSREG_##name##_OFFSET)) | SYSREG_BF(name,value)) #define SYSREG_BIT(name) \ (1 << SYSREG_##name##_OFFSET) #define SYSREG_BF(name,value) \ (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \ << SYSREG_##name##_OFFSET) #define SYSREG_BFEXT(name,value)\ (((value) >> SYSREG_##name##_OFFSET) \ & ((1 << SYSREG_##name##_SIZE) - 1)) #define SYSREG_BFINS(name,value,old) \ (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \ << SYSREG_##name##_OFFSET)) \ | SYSREG_BF(name,value)) /* Register access macros */ #ifdef __CHECKER__ extern unsigned long __builtin_mfsr(unsigned long reg); extern void __builtin_mtsr(unsigned long reg, unsigned long value); #endif /* Register access macros */ #define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg) #define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value) #endif /* __ASM_AVR32_SYSREG_H__ */ #endif /* __ASM_AVR32_SYSREG_H */