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Commit 53478c07 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Halt GBIF GX traffic for GPU with no GMU"

parents 4ba483c5 ab06836a

drivers/gpu/msm/a6xx_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -404,6 +404,8 @@ 


#define A6XX_RBBM_VBIF_CLIENT_QOS_CNTL   0x00010

#define A6XX_RBBM_GBIF_CLIENT_QOS_CNTL   0x00011

#define A6XX_RBBM_GBIF_HALT              0x00016

#define A6XX_RBBM_GBIF_HALT_ACK          0x00017

#define A6XX_RBBM_GPR0_CNTL              0x00018

#define A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0001f

#define A6XX_RBBM_INT_CLEAR_CMD          0x00037
@@ -828,6 +830,7 @@ 


#define A6XX_GBIF_CLIENT_HALT_MASK        BIT(0)

#define A6XX_GBIF_ARB_HALT_MASK           BIT(1)

#define A6XX_GBIF_GX_HALT_MASK            BIT(0)



#define A6XX_GBIF_PERF_PWR_CNT_EN         0x3cc0

#define A6XX_GBIF_PERF_CNT_SEL            0x3cc2

drivers/gpu/msm/adreno.c

+22 −0
Original line number Diff line number Diff line
@@ -1623,6 +1623,28 @@ int adreno_clear_pending_transactions(struct kgsl_device *device) 


	if (adreno_has_gbif(adreno_dev)) {



		/* This is taken care by GMU firmware if GMU is enabled */

		if (!gmu_core_gpmu_isenabled(device)) {

			/* Halt GBIF GX traffic and poll for halt ack */

			if (adreno_is_a615_family(adreno_dev)) {

				adreno_writereg(adreno_dev,

					ADRENO_REG_RBBM_GPR0_CNTL,

					GBIF_HALT_REQUEST);

				ret = adreno_wait_for_halt_ack(device,

					A6XX_RBBM_VBIF_GX_RESET_STATUS,

					VBIF_RESET_ACK_MASK);

			} else {

				adreno_writereg(adreno_dev,

					ADRENO_REG_RBBM_GBIF_HALT,

					gpudev->gbif_gx_halt_mask);

				ret = adreno_wait_for_halt_ack(device,

					ADRENO_REG_RBBM_GBIF_HALT_ACK,

					gpudev->gbif_gx_halt_mask);

			}

			if (ret)

				return ret;

		}



		/* Halt new client requests */

		adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT,

				gpudev->gbif_client_halt_mask);

drivers/gpu/msm/adreno.h

+14 −1
Original line number Diff line number Diff line
@@ -684,6 +684,8 @@ enum adreno_regs { 
	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

	ADRENO_REG_RBBM_GPR0_CNTL,

	ADRENO_REG_RBBM_GBIF_HALT,

	ADRENO_REG_RBBM_GBIF_HALT_ACK,

	ADRENO_REG_RBBM_VBIF_GX_RESET_STATUS,

	ADRENO_REG_VBIF_XIN_HALT_CTRL0,

	ADRENO_REG_VBIF_XIN_HALT_CTRL1,
@@ -875,6 +877,7 @@ struct adreno_gpudev { 
	unsigned int vbif_xin_halt_ctrl0_mask;

	unsigned int gbif_client_halt_mask;

	unsigned int gbif_arb_halt_mask;

	unsigned int gbif_gx_halt_mask;

	/* GPU specific function hooks */

	void (*irq_trace)(struct adreno_device *adreno_dev,

				unsigned int status);
@@ -1834,8 +1837,18 @@ static inline int adreno_wait_for_halt_ack(struct kgsl_device *device, 


static inline void adreno_deassert_gbif_halt(struct adreno_device *adreno_dev)

{

	if (adreno_has_gbif(adreno_dev))

	if (adreno_has_gbif(adreno_dev)) {

		adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT, 0x0);



		/*

		 * Release GBIF GX halt. For A615 family, GPU GX halt

		 * will be cleared automatically on reset.

		 */

		if (!gmu_core_gpmu_isenabled(KGSL_DEVICE(adreno_dev)) &&

			!adreno_is_a615_family(adreno_dev))

			adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_GBIF_HALT, 0x0);

	}

}

void adreno_gmu_clear_and_unmask_irqs(struct adreno_device *adreno_dev);

void adreno_gmu_mask_and_clear_irqs(struct adreno_device *adreno_dev);

drivers/gpu/msm/adreno_a6xx.c

+5 −0
Original line number Diff line number Diff line
@@ -2381,6 +2381,7 @@ static void a6xx_platform_setup(struct adreno_device *adreno_dev) 


		gpudev->gbif_client_halt_mask = A6XX_GBIF_CLIENT_HALT_MASK;

		gpudev->gbif_arb_halt_mask = A6XX_GBIF_ARB_HALT_MASK;

		gpudev->gbif_gx_halt_mask = A6XX_GBIF_GX_HALT_MASK;

	} else

		gpudev->vbif_xin_halt_ctrl0_mask =

				A6XX_VBIF_XIN_HALT_CTRL0_MASK;
@@ -2484,6 +2485,10 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_GPR0_CNTL, A6XX_RBBM_GPR0_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_VBIF_GX_RESET_STATUS,

				A6XX_RBBM_VBIF_GX_RESET_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_GBIF_HALT,

				A6XX_RBBM_GBIF_HALT),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_GBIF_HALT_ACK,

				A6XX_RBBM_GBIF_HALT_ACK),

	ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT, A6XX_GBIF_HALT),

	ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT_ACK, A6XX_GBIF_HALT_ACK),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,