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Commit 52246445 authored by poonam aggrwal's avatar poonam aggrwal Committed by Scott Wood
Browse files

powerpc/b4860: Renamed the L2 caches 



To make provision for more than one L2 caches in the system, change the
name from L2 to L2_1; same as in T4 platforms.
* Also remove the L2 entry from common file
  "arch/powerpc/boot/dts/fsl/b4si-post.dtsi"
  Keep them only in separate files for b4860 and b4420.

Signed-off-by: default avatarShaveta Leekha <shaveta@freescale.com>
Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent dc37374b

arch/powerpc/boot/dts/fsl/b4420si-post.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -89,7 +89,9 @@ 
		compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";

	};



	L2: l2-cache-controller@c20000 {

	L2_1: l2-cache-controller@c20000 {

		compatible = "fsl,b4420-l2-cache-controller";

		reg = <0xc20000 0x40000>;

		next-level-cache = <&cpc>;

	};

};

arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -65,14 +65,14 @@ 
			device_type = "cpu";

			reg = <0 1>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			reg = <2 3>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

	};

arch/powerpc/boot/dts/fsl/b4860si-post.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -258,7 +258,9 @@ 
		compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";

	};



	L2: l2-cache-controller@c20000 {

	L2_1: l2-cache-controller@c20000 {

		compatible = "fsl,b4860-l2-cache-controller";

		reg = <0xc20000 0x40000>;

		next-level-cache = <&cpc>;

	};

};

arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -65,28 +65,28 @@ 
			device_type = "cpu";

			reg = <0 1>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			reg = <2 3>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

		cpu2: PowerPC,e6500@4 {

			device_type = "cpu";

			reg = <4 5>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

		cpu3: PowerPC,e6500@6 {

			device_type = "cpu";

			reg = <6 7>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2_1>;

			fsl,portid-mapping = <0x80000000>;

		};

	};

arch/powerpc/boot/dts/fsl/b4si-post.dtsi

+0 −6
Original line number Diff line number Diff line
@@ -465,10 +465,4 @@ 
	bman: bman@31a000 {

		interrupts = <16 2 1 29>;

	};



	L2: l2-cache-controller@c20000 {

		compatible = "fsl,b4-l2-cache-controller";

		reg = <0xc20000 0x1000>;

		next-level-cache = <&cpc>;

	};

};