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Commit 51a01b8c authored by Dharageswari R's avatar Dharageswari R Committed by Mark Brown
Browse files

ASoC: Intel: Skylake: Disable SRAM Retention before D3 



SW needs to set the PGCTL.LSRMD = 1 to disable LPSRAM retention
feature,otherwise it may lead to SRAM ECC Errors.

Signed-off-by: default avatarDharageswari R <dharageswari.r@intel.com>
Signed-off-by: default avatarJeeja KP <jeeja.kp@intel.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1ae7ca04

sound/soc/intel/skylake/skl.c

+3 −0
Original line number Diff line number Diff line
@@ -186,6 +186,7 @@ static int _skl_suspend(struct hdac_ext_bus *ebus) 
{

	struct skl *skl = ebus_to_skl(ebus);

	struct hdac_bus *bus = ebus_to_hbus(ebus);

	struct pci_dev *pci = to_pci_dev(bus->dev);

	int ret;



	snd_hdac_ext_bus_link_power_down_all(ebus);
@@ -195,6 +196,8 @@ static int _skl_suspend(struct hdac_ext_bus *ebus) 
		return ret;



	snd_hdac_bus_stop_chip(bus);

	update_pci_dword(pci, AZX_PCIREG_PGCTL,

		AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK);

	skl_enable_miscbdcge(bus->dev, false);

	snd_hdac_bus_enter_link_reset(bus);

	skl_enable_miscbdcge(bus->dev, true);

sound/soc/intel/skylake/skl.h

+2 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ 
#define AZX_REG_VS_SDXEFIFOS_XBASE	0x1094

#define AZX_REG_VS_SDXEFIFOS_XINTERVAL	0x20



#define AZX_PCIREG_PGCTL		0x44

#define AZX_PGCTL_LSRMD_MASK		(1 << 4)

#define AZX_PCIREG_CGCTL		0x48

#define AZX_CGCTL_MISCBDCGE_MASK	(1 << 6)