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Commit 515f1a20 authored by Antoine Tenart's avatar Antoine Tenart Committed by Sebastian Hesselbarth
Browse files

clk: berlin: add cpuclk 



Add cpuclk in the Berlin BG2Q clock driver. This clk has a divider
fixed to 1.

Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
parent 0f0ebb13

drivers/clk/berlin/bg2q.c

+7 −7
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ 
#define REG_SDIO0XIN_CLKCTL	0x0158

#define REG_SDIO1XIN_CLKCTL	0x015c



#define	MAX_CLKS 27

#define	MAX_CLKS 28

static struct clk *clks[MAX_CLKS];

static struct clk_onecell_data clk_data;

static DEFINE_SPINLOCK(lock);
@@ -356,13 +356,13 @@ static void __init berlin2q_clock_setup(struct device_node *np) 
			    gd->bit_idx, 0, &lock);

	}



	/*

	 * twdclk is derived from cpu/3

	 * TODO: use cpupll until cpuclk is not available

	 */

	/* cpuclk divider is fixed to 1 */

	clks[CLKID_CPU] =

		clk_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL],

					  0, 1, 1);

	/* twdclk is derived from cpu/3 */

	clks[CLKID_TWD] =

		clk_register_fixed_factor(NULL, "twd", clk_names[CPUPLL],

					  0, 1, 3);

		clk_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);



	/* check for errors on leaf clocks */

	for (n = 0; n < MAX_CLKS; n++) {