Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 510c2558 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: fix pcie max lane define error

parent e71b7ae6
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ typedef enum PP_PCIEGen PP_PCIEGen;
#define PP_Min_PCIEGen     PP_PCIEGen1
#define PP_Max_PCIEGen     PP_PCIEGen3
#define PP_Min_PCIELane    1
#define PP_Max_PCIELane    32
#define PP_Max_PCIELane    16

enum phm_clock_Type {
	PHM_DispClock = 1,