hisi_sas: Add v1 hardware register definitions

#include "hisi_sas.h"

#define DRV_NAME "hisi_sas_v1_hw"

/* global registers need init*/

#define DLVRY_QUEUE_ENABLE		0x0

#define IOST_BASE_ADDR_LO		0x8

#define IOST_BASE_ADDR_HI		0xc

#define ITCT_BASE_ADDR_LO		0x10

#define ITCT_BASE_ADDR_HI		0x14

#define BROKEN_MSG_ADDR_LO		0x18

#define BROKEN_MSG_ADDR_HI		0x1c

#define PHY_CONTEXT			0x20

#define PHY_STATE			0x24

#define PHY_PORT_NUM_MA			0x28

#define PORT_STATE			0x2c

#define PHY_CONN_RATE			0x30

#define HGC_TRANS_TASK_CNT_LIMIT	0x38

#define AXI_AHB_CLK_CFG			0x3c

#define HGC_SAS_TXFAIL_RETRY_CTRL	0x84

#define HGC_GET_ITV_TIME		0x90

#define DEVICE_MSG_WORK_MODE		0x94

#define I_T_NEXUS_LOSS_TIME		0xa0

#define BUS_INACTIVE_LIMIT_TIME		0xa8

#define REJECT_TO_OPEN_LIMIT_TIME	0xac

#define CFG_AGING_TIME			0xbc

#define CFG_AGING_TIME_ITCT_REL_OFF	0

#define CFG_AGING_TIME_ITCT_REL_MSK	(0x1 << CFG_AGING_TIME_ITCT_REL_OFF)

#define HGC_DFX_CFG2			0xc0

#define FIS_LIST_BADDR_L		0xc4

#define CFG_1US_TIMER_TRSH		0xcc

#define CFG_SAS_CONFIG			0xd4

#define HGC_IOST_ECC_ADDR		0x140

#define HGC_IOST_ECC_ADDR_BAD_OFF	16

#define HGC_IOST_ECC_ADDR_BAD_MSK	(0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF)

#define HGC_DQ_ECC_ADDR			0x144

#define HGC_DQ_ECC_ADDR_BAD_OFF		16

#define HGC_DQ_ECC_ADDR_BAD_MSK		(0xfff << HGC_DQ_ECC_ADDR_BAD_OFF)

#define HGC_INVLD_DQE_INFO		0x148

#define HGC_INVLD_DQE_INFO_DQ_OFF	0

#define HGC_INVLD_DQE_INFO_DQ_MSK	(0xffff << HGC_INVLD_DQE_INFO_DQ_OFF)

#define HGC_INVLD_DQE_INFO_TYPE_OFF	16

#define HGC_INVLD_DQE_INFO_TYPE_MSK	(0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF)

#define HGC_INVLD_DQE_INFO_FORCE_OFF	17

#define HGC_INVLD_DQE_INFO_FORCE_MSK	(0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF)

#define HGC_INVLD_DQE_INFO_PHY_OFF	18

#define HGC_INVLD_DQE_INFO_PHY_MSK	(0x1 << HGC_INVLD_DQE_INFO_PHY_OFF)

#define HGC_INVLD_DQE_INFO_ABORT_OFF	19

#define HGC_INVLD_DQE_INFO_ABORT_MSK	(0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF)

#define HGC_INVLD_DQE_INFO_IPTT_OF_OFF	20

#define HGC_INVLD_DQE_INFO_IPTT_OF_MSK	(0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF)

#define HGC_INVLD_DQE_INFO_SSP_ERR_OFF	21

#define HGC_INVLD_DQE_INFO_SSP_ERR_MSK	(0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF)

#define HGC_INVLD_DQE_INFO_OFL_OFF	22

#define HGC_INVLD_DQE_INFO_OFL_MSK	(0x1 << HGC_INVLD_DQE_INFO_OFL_OFF)

#define HGC_ITCT_ECC_ADDR		0x150

#define HGC_ITCT_ECC_ADDR_BAD_OFF	16

#define HGC_ITCT_ECC_ADDR_BAD_MSK	(0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF)

#define HGC_AXI_FIFO_ERR_INFO		0x154

#define INT_COAL_EN			0x1bc

#define OQ_INT_COAL_TIME		0x1c0

#define OQ_INT_COAL_CNT			0x1c4

#define ENT_INT_COAL_TIME		0x1c8

#define ENT_INT_COAL_CNT		0x1cc

#define OQ_INT_SRC			0x1d0

#define OQ_INT_SRC_MSK			0x1d4

#define ENT_INT_SRC1			0x1d8

#define ENT_INT_SRC2			0x1dc

#define ENT_INT_SRC2_DQ_CFG_ERR_OFF	25

#define ENT_INT_SRC2_DQ_CFG_ERR_MSK	(0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF)

#define ENT_INT_SRC2_CQ_CFG_ERR_OFF	27

#define ENT_INT_SRC2_CQ_CFG_ERR_MSK	(0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF)

#define ENT_INT_SRC2_AXI_WRONG_INT_OFF	28

#define ENT_INT_SRC2_AXI_WRONG_INT_MSK	(0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF)

#define ENT_INT_SRC2_AXI_OVERLF_INT_OFF	29

#define ENT_INT_SRC2_AXI_OVERLF_INT_MSK	(0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF)

#define ENT_INT_SRC_MSK1		0x1e0

#define ENT_INT_SRC_MSK2		0x1e4

#define SAS_ECC_INTR			0x1e8

#define SAS_ECC_INTR_DQ_ECC1B_OFF	0

#define SAS_ECC_INTR_DQ_ECC1B_MSK	(0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF)

#define SAS_ECC_INTR_DQ_ECCBAD_OFF	1

#define SAS_ECC_INTR_DQ_ECCBAD_MSK	(0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF)

#define SAS_ECC_INTR_IOST_ECC1B_OFF	2

#define SAS_ECC_INTR_IOST_ECC1B_MSK	(0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF)

#define SAS_ECC_INTR_IOST_ECCBAD_OFF	3

#define SAS_ECC_INTR_IOST_ECCBAD_MSK	(0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF)

#define SAS_ECC_INTR_ITCT_ECC1B_OFF	4

#define SAS_ECC_INTR_ITCT_ECC1B_MSK	(0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF)

#define SAS_ECC_INTR_ITCT_ECCBAD_OFF	5

#define SAS_ECC_INTR_ITCT_ECCBAD_MSK	(0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF)

#define SAS_ECC_INTR_MSK		0x1ec

#define HGC_ERR_STAT_EN			0x238

#define DLVRY_Q_0_BASE_ADDR_LO		0x260

#define DLVRY_Q_0_BASE_ADDR_HI		0x264

#define DLVRY_Q_0_DEPTH			0x268

#define DLVRY_Q_0_WR_PTR		0x26c

#define DLVRY_Q_0_RD_PTR		0x270

#define COMPL_Q_0_BASE_ADDR_LO		0x4e0

#define COMPL_Q_0_BASE_ADDR_HI		0x4e4

#define COMPL_Q_0_DEPTH			0x4e8

#define COMPL_Q_0_WR_PTR		0x4ec

#define COMPL_Q_0_RD_PTR		0x4f0

#define HGC_ECC_ERR			0x7d0

/* phy registers need init */

#define PORT_BASE			(0x800)

#define PHY_CFG				(PORT_BASE + 0x0)

#define PHY_CFG_ENA_OFF			0

#define PHY_CFG_ENA_MSK			(0x1 << PHY_CFG_ENA_OFF)

#define PHY_CFG_DC_OPT_OFF		2

#define PHY_CFG_DC_OPT_MSK		(0x1 << PHY_CFG_DC_OPT_OFF)

#define PROG_PHY_LINK_RATE		(PORT_BASE + 0xc)

#define PROG_PHY_LINK_RATE_MAX_OFF	0

#define PROG_PHY_LINK_RATE_MAX_MSK	(0xf << PROG_PHY_LINK_RATE_MAX_OFF)

#define PROG_PHY_LINK_RATE_MIN_OFF	4

#define PROG_PHY_LINK_RATE_MIN_MSK	(0xf << PROG_PHY_LINK_RATE_MIN_OFF)

#define PROG_PHY_LINK_RATE_OOB_OFF	8

#define PROG_PHY_LINK_RATE_OOB_MSK	(0xf << PROG_PHY_LINK_RATE_OOB_OFF)

#define PHY_CTRL			(PORT_BASE + 0x14)

#define PHY_CTRL_RESET_OFF		0

#define PHY_CTRL_RESET_MSK		(0x1 << PHY_CTRL_RESET_OFF)

#define PHY_RATE_NEGO			(PORT_BASE + 0x30)

#define PHY_PCN				(PORT_BASE + 0x44)

#define SL_TOUT_CFG			(PORT_BASE + 0x8c)

#define SL_CONTROL			(PORT_BASE + 0x94)

#define SL_CONTROL_NOTIFY_EN_OFF	0

#define SL_CONTROL_NOTIFY_EN_MSK	(0x1 << SL_CONTROL_NOTIFY_EN_OFF)

#define TX_ID_DWORD0			(PORT_BASE + 0x9c)

#define TX_ID_DWORD1			(PORT_BASE + 0xa0)

#define TX_ID_DWORD2			(PORT_BASE + 0xa4)

#define TX_ID_DWORD3			(PORT_BASE + 0xa8)

#define TX_ID_DWORD4			(PORT_BASE + 0xaC)

#define TX_ID_DWORD5			(PORT_BASE + 0xb0)

#define TX_ID_DWORD6			(PORT_BASE + 0xb4)

#define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)

#define RX_IDAF_DWORD1			(PORT_BASE + 0xc8)

#define RX_IDAF_DWORD2			(PORT_BASE + 0xcc)

#define RX_IDAF_DWORD3			(PORT_BASE + 0xd0)

#define RX_IDAF_DWORD4			(PORT_BASE + 0xd4)

#define RX_IDAF_DWORD5			(PORT_BASE + 0xd8)

#define RX_IDAF_DWORD6			(PORT_BASE + 0xdc)

#define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)

#define DONE_RECEIVED_TIME		(PORT_BASE + 0x12c)

#define CON_CFG_DRIVER			(PORT_BASE + 0x130)

#define PHY_CONFIG2			(PORT_BASE + 0x1a8)

#define PHY_CONFIG2_FORCE_TXDEEMPH_OFF	3

#define PHY_CONFIG2_FORCE_TXDEEMPH_MSK	(0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)

#define PHY_CONFIG2_TX_TRAIN_COMP_OFF	24

#define PHY_CONFIG2_TX_TRAIN_COMP_MSK	(0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF)

#define CHL_INT0			(PORT_BASE + 0x1b0)

#define CHL_INT0_PHYCTRL_NOTRDY_OFF	0

#define CHL_INT0_PHYCTRL_NOTRDY_MSK	(0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF)

#define CHL_INT0_SN_FAIL_NGR_OFF	2

#define CHL_INT0_SN_FAIL_NGR_MSK	(0x1 << CHL_INT0_SN_FAIL_NGR_OFF)

#define CHL_INT0_DWS_LOST_OFF		4

#define CHL_INT0_DWS_LOST_MSK		(0x1 << CHL_INT0_DWS_LOST_OFF)

#define CHL_INT0_SL_IDAF_FAIL_OFF	10

#define CHL_INT0_SL_IDAF_FAIL_MSK	(0x1 << CHL_INT0_SL_IDAF_FAIL_OFF)

#define CHL_INT0_ID_TIMEOUT_OFF		11

#define CHL_INT0_ID_TIMEOUT_MSK		(0x1 << CHL_INT0_ID_TIMEOUT_OFF)

#define CHL_INT0_SL_OPAF_FAIL_OFF	12

#define CHL_INT0_SL_OPAF_FAIL_MSK	(0x1 << CHL_INT0_SL_OPAF_FAIL_OFF)

#define CHL_INT0_SL_PS_FAIL_OFF		21

#define CHL_INT0_SL_PS_FAIL_MSK		(0x1 << CHL_INT0_SL_PS_FAIL_OFF)

#define CHL_INT1			(PORT_BASE + 0x1b4)

#define CHL_INT2			(PORT_BASE + 0x1b8)

#define CHL_INT2_SL_RX_BC_ACK_OFF	2

#define CHL_INT2_SL_RX_BC_ACK_MSK	(0x1 << CHL_INT2_SL_RX_BC_ACK_OFF)

#define CHL_INT2_SL_PHY_ENA_OFF		6

#define CHL_INT2_SL_PHY_ENA_MSK		(0x1 << CHL_INT2_SL_PHY_ENA_OFF)

#define CHL_INT0_MSK			(PORT_BASE + 0x1bc)

#define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF	0

#define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK	(0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF)

#define CHL_INT1_MSK			(PORT_BASE + 0x1c0)

#define CHL_INT2_MSK			(PORT_BASE + 0x1c4)

#define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)

#define DMA_TX_STATUS			(PORT_BASE + 0x2d0)

#define DMA_TX_STATUS_BUSY_OFF		0

#define DMA_TX_STATUS_BUSY_MSK		(0x1 << DMA_TX_STATUS_BUSY_OFF)

#define DMA_RX_STATUS			(PORT_BASE + 0x2e8)

#define DMA_RX_STATUS_BUSY_OFF		0

#define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)

#define AXI_CFG				0x5100

#define RESET_VALUE			0x7ffff

/* HW dma structures */

/* Delivery queue header */

/* dw0 */

#define CMD_HDR_RESP_REPORT_OFF		5

#define CMD_HDR_RESP_REPORT_MSK		0x20

#define CMD_HDR_TLR_CTRL_OFF		6

#define CMD_HDR_TLR_CTRL_MSK		0xc0

#define CMD_HDR_PORT_OFF		17

#define CMD_HDR_PORT_MSK		0xe0000

#define CMD_HDR_PRIORITY_OFF		27

#define CMD_HDR_PRIORITY_MSK		0x8000000

#define CMD_HDR_MODE_OFF		28

#define CMD_HDR_MODE_MSK		0x10000000

#define CMD_HDR_CMD_OFF			29

#define CMD_HDR_CMD_MSK			0xe0000000

/* dw1 */

#define CMD_HDR_VERIFY_DTL_OFF		10

#define CMD_HDR_VERIFY_DTL_MSK		0x400

#define CMD_HDR_SSP_FRAME_TYPE_OFF	13

#define CMD_HDR_SSP_FRAME_TYPE_MSK	0xe000

#define CMD_HDR_DEVICE_ID_OFF		16

#define CMD_HDR_DEVICE_ID_MSK		0xffff0000

/* dw2 */

#define CMD_HDR_CFL_OFF			0

#define CMD_HDR_CFL_MSK			0x1ff

#define CMD_HDR_MRFL_OFF		15

#define CMD_HDR_MRFL_MSK		0xff8000

#define CMD_HDR_FIRST_BURST_OFF		25

#define CMD_HDR_FIRST_BURST_MSK		0x2000000

/* dw3 */

#define CMD_HDR_IPTT_OFF		0

#define CMD_HDR_IPTT_MSK		0xffff

/* dw6 */

#define CMD_HDR_DATA_SGL_LEN_OFF	16

#define CMD_HDR_DATA_SGL_LEN_MSK	0xffff0000

/* Completion header */

#define CMPLT_HDR_IPTT_OFF		0

#define CMPLT_HDR_IPTT_MSK		(0xffff << CMPLT_HDR_IPTT_OFF)

#define CMPLT_HDR_CMD_CMPLT_OFF		17

#define CMPLT_HDR_CMD_CMPLT_MSK		(0x1 << CMPLT_HDR_CMD_CMPLT_OFF)

#define CMPLT_HDR_ERR_RCRD_XFRD_OFF	18

#define CMPLT_HDR_ERR_RCRD_XFRD_MSK	(0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF)

#define CMPLT_HDR_RSPNS_XFRD_OFF	19

#define CMPLT_HDR_RSPNS_XFRD_MSK	(0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)

#define CMPLT_HDR_IO_CFG_ERR_OFF	27

#define CMPLT_HDR_IO_CFG_ERR_MSK	(0x1 << CMPLT_HDR_IO_CFG_ERR_OFF)

/* ITCT header */

/* qw0 */

#define ITCT_HDR_DEV_TYPE_OFF		0

#define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)

#define ITCT_HDR_VALID_OFF		2

#define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)

#define ITCT_HDR_BREAK_REPLY_ENA_OFF	3

#define ITCT_HDR_BREAK_REPLY_ENA_MSK	(0x1 << ITCT_HDR_BREAK_REPLY_ENA_OFF)

#define ITCT_HDR_AWT_CONTROL_OFF	4

#define ITCT_HDR_AWT_CONTROL_MSK	(0x1 << ITCT_HDR_AWT_CONTROL_OFF)

#define ITCT_HDR_MAX_CONN_RATE_OFF	5

#define ITCT_HDR_MAX_CONN_RATE_MSK	(0xf << ITCT_HDR_MAX_CONN_RATE_OFF)

#define ITCT_HDR_VALID_LINK_NUM_OFF	9

#define ITCT_HDR_VALID_LINK_NUM_MSK	(0xf << ITCT_HDR_VALID_LINK_NUM_OFF)

#define ITCT_HDR_PORT_ID_OFF		13

#define ITCT_HDR_PORT_ID_MSK		(0x7 << ITCT_HDR_PORT_ID_OFF)

#define ITCT_HDR_SMP_TIMEOUT_OFF	16

#define ITCT_HDR_SMP_TIMEOUT_MSK	(0xffff << ITCT_HDR_SMP_TIMEOUT_OFF)

#define ITCT_HDR_MAX_BURST_BYTES_OFF	16

#define ITCT_HDR_MAX_BURST_BYTES_MSK	(0xffffffff << \

					ITCT_MAX_BURST_BYTES_OFF)

/* qw1 */

#define ITCT_HDR_MAX_SAS_ADDR_OFF	0

#define ITCT_HDR_MAX_SAS_ADDR_MSK	(0xffffffffffffffff << \

					ITCT_HDR_MAX_SAS_ADDR_OFF)

/* qw2 */

#define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF	0

#define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK	(0xffff << \

					ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)

#define ITCT_HDR_BUS_INACTIVE_TL_OFF	16

#define ITCT_HDR_BUS_INACTIVE_TL_MSK	(0xffff << \

					ITCT_HDR_BUS_INACTIVE_TL_OFF)

#define ITCT_HDR_MAX_CONN_TL_OFF	32

#define ITCT_HDR_MAX_CONN_TL_MSK	(0xffff << \

					ITCT_HDR_MAX_CONN_TL_OFF)

#define ITCT_HDR_REJ_OPEN_TL_OFF	48

#define ITCT_HDR_REJ_OPEN_TL_MSK	(0xffff << \

					ITCT_REJ_OPEN_TL_OFF)

/* Err record header */

#define ERR_HDR_DMA_TX_ERR_TYPE_OFF	0

#define ERR_HDR_DMA_TX_ERR_TYPE_MSK	(0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF)

#define ERR_HDR_DMA_RX_ERR_TYPE_OFF	16

#define ERR_HDR_DMA_RX_ERR_TYPE_MSK	(0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF)

struct hisi_sas_complete_v1_hdr {

	__le32 data;

};

enum {

	HISI_SAS_PHY_BCAST_ACK = 0,

	HISI_SAS_PHY_SL_PHY_ENABLED,

	HISI_SAS_PHY_INT_ABNORMAL,

	HISI_SAS_PHY_INT_NR

};

enum {

	DMA_TX_ERR_BASE = 0x0,

	DMA_RX_ERR_BASE = 0x100,

	TRANS_TX_FAIL_BASE = 0x200,

	TRANS_RX_FAIL_BASE = 0x300,

	/* dma tx */

	DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */

	DMA_TX_DIF_APP_ERR, /* 0x1 */

	DMA_TX_DIF_RPP_ERR, /* 0x2 */

	DMA_TX_AXI_BUS_ERR, /* 0x3 */

	DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */

	DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */

	DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */

	DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */

	DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */

	DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */

	/* dma rx */

	DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */

	DMA_RX_DIF_CRC_ERR, /* 0x101 */

	DMA_RX_DIF_APP_ERR, /* 0x102 */

	DMA_RX_DIF_RPP_ERR, /* 0x103 */

	DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */

	DMA_RX_AXI_BUS_ERR, /* 0x105 */

	DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */

	DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */

	DMA_RX_DATA_OFFSET_ERR, /* 0x108 */

	DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */

	DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */

	DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */

	DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */

	/* trans tx */

	TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */

	TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */

	TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */

	TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */

	TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */

	TRANS_TX_RSVD1_ERR, /* 0x205 */

	TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */

	TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */

	TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */

	TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */

	TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */

	TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */

	TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */

	TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */

	TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */

	TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */

	TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */

	TRANS_TX_RSVD2_ERR, /* 0x211 */

	TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */

	TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */

	TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */

	TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */

	TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */

	TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */

	TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */

	TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */

	TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */

	TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */

	TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */

	TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */

	TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */

	TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */

	/* trans rx */

	TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */

	TRANS_RX_FRAME_DONE_ERR, /* 0x301 */

	TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */

	TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */

	TRANS_RX_RSVD0_ERR, /* 0x304 */

	TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */

	TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */

	TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */

	TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */

	TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */

	TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */

	TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */

	TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */

	TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */

	TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */

	TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */

	TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */

	TRANS_RX_BAD_HASH_ERR, /* 0x311 */

	TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */

	TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */

	TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */

	TRANS_RX_NO_BALANCE_ERR, /* 0x315 */

	TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */

	TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */

	TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */

	TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */

	TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */

};

#define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)

#define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)

#define HISI_SAS_FATAL_INT_NR (2)

#define HISI_SAS_MAX_INT_NR \

	(HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\

	HISI_SAS_FATAL_INT_NR)

static const struct hisi_sas_hw hisi_sas_v1_hw = {

	.complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr),

};