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Commit 5080c7e9 authored by Yotam Gigi's avatar Yotam Gigi Committed by David S. Miller
Browse files

mlxsw: reg: Add the Router Interface Group Version 2 register 



The RIGR-V2 register is used to add, remove and query egress interface list
of a multicast forwarding entry and it will be used by the multicast
router offloading logic.

Signed-off-by: default avatarYotam Gigi <yotamg@mellanox.com>
Reviewed-by: default avatarIdo Schimmel <idosch@mellanox.com>
Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 46a7054e

drivers/net/ethernet/mellanox/mlxsw/reg.h

+83 −0
Original line number Diff line number Diff line
@@ -5646,6 +5646,88 @@ mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 
	mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);

}



/* RIGR-V2 - Router Interface Group Register Version 2

 * ---------------------------------------------------

 * The RIGR_V2 register is used to add, remove and query egress interface list

 * of a multicast forwarding entry.

 */

#define MLXSW_REG_RIGR2_ID 0x8023

#define MLXSW_REG_RIGR2_LEN 0xB0



#define MLXSW_REG_RIGR2_MAX_ERIFS 32



MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);



/* reg_rigr2_rigr_index

 * KVD Linear index.

 * Access: Index

 */

MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);



/* reg_rigr2_vnext

 * Next RIGR Index is valid.

 * Access: RW

 */

MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);



/* reg_rigr2_next_rigr_index

 * Next RIGR Index. The index is to the KVD linear.

 * Reserved when vnxet = '0'.

 * Access: RW

 */

MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);



/* reg_rigr2_vrmid

 * RMID Index is valid.

 * Access: RW

 */

MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);



/* reg_rigr2_rmid_index

 * RMID Index.

 * Range 0 .. max_mid - 1

 * Reserved when vrmid = '0'.

 * The index is to the Port Group Table (PGT)

 * Access: RW

 */

MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);



/* reg_rigr2_erif_entry_v

 * Egress Router Interface is valid.

 * Note that low-entries must be set if high-entries are set. For

 * example: if erif_entry[2].v is set then erif_entry[1].v and

 * erif_entry[0].v must be set.

 * Index can be from 0 to cap_mc_erif_list_entries-1

 * Access: RW

 */

MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);



/* reg_rigr2_erif_entry_erif

 * Egress Router Interface.

 * Valid range is from 0 to cap_max_router_interfaces - 1

 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1

 * Access: RW

 */

MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);



static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,

					bool vnext, u32 next_rigr_index)

{

	MLXSW_REG_ZERO(rigr2, payload);

	mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);

	mlxsw_reg_rigr2_vnext_set(payload, vnext);

	mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);

	mlxsw_reg_rigr2_vrmid_set(payload, 0);

	mlxsw_reg_rigr2_rmid_index_set(payload, 0);

}



static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,

						   bool v, u16 erif)

{

	mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);

	mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);

}



/* MFCR - Management Fan Control Register

 * --------------------------------------

 * This register controls the settings of the Fan Speed PWM mechanism.
@@ -6917,6 +6999,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 
	MLXSW_REG(rauht),

	MLXSW_REG(raleu),

	MLXSW_REG(rauhtd),

	MLXSW_REG(rigr2),

	MLXSW_REG(mfcr),

	MLXSW_REG(mfsc),

	MLXSW_REG(mfsm),