Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 506a6c77 authored by Venkat Chinta's avatar Venkat Chinta
Browse files

msm: camera: vfe: Add missing data for PDLIB



This change adds missing reg offsets and data needed to
enable PDLIB CAMIF.

Change-Id: I7842d3515b47ef3f78321d3457b1714193ed8b8a
Signed-off-by: default avatarVenkat Chinta <vchinta@codeaurora.org>
parent f5f31790
Loading
Loading
Loading
Loading
+6 −1
Original line number Diff line number Diff line
@@ -57,10 +57,11 @@ static struct cam_vfe_camif_ver3_pp_clc_reg vfe480_camif_reg = {

static struct cam_vfe_camif_ver3_reg_data vfe_480_camif_reg_data = {
	.pp_extern_reg_update_shift      = 4,
	.lcr_extern_reg_update_shift     = 16,
	.dual_pd_extern_reg_update_shift = 17,
	.extern_reg_update_mask          = 1,
	.dual_ife_pix_en_shift           = 3,
	.operating_mode_shift            = 11,
	.input_mux_sel_shift             = 5,
	.pixel_pattern_shift             = 24,
	.pixel_pattern_mask              = 0x7,
	.dsp_mode_shift                  = 24,
@@ -198,6 +199,7 @@ static struct cam_vfe_camif_lite_ver3_reg vfe480_camif_lcr = {
	.lite_debug_0               = 0xA1F4,
	.lite_test_bus_ctrl         = 0xA1F8,
	.camif_lite_spare           = 0xA1FC,
	.reg_update_cmd             = 0x0034,
};

static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_lcr_reg_data = {
@@ -223,10 +225,13 @@ static struct cam_vfe_camif_lite_ver3_reg vfe480_camif_pd = {
	.lite_debug_0               = 0xA5F4,
	.lite_test_bus_ctrl         = 0xA5F8,
	.camif_lite_spare           = 0xA5FC,
	.reg_update_cmd             = 0x0034,
};

static struct cam_vfe_camif_lite_ver3_reg_data vfe480_camif_pd_reg_data = {
	.extern_reg_update_shift    = 17,
	.operating_mode_shift       = 13,
	.input_mux_sel_shift        = 31,
	.reg_update_cmd_data        = 0x20,
	.epoch_line_cfg             = 0x00140014,
	.sof_irq_mask               = 0x10000,
+4 −2
Original line number Diff line number Diff line
@@ -129,11 +129,13 @@ static int cam_vfe_camif_lite_resource_start(
	val = cam_io_r_mb(rsrc_data->mem_base +
		rsrc_data->common_reg->core_cfg_0);

	if (camif_lite_res->res_id == CAM_ISP_HW_VFE_IN_PDLIB &&
		camif_lite_res->res_id == CAM_ISP_HW_VFE_IN_LCR &&
	if (camif_lite_res->res_id == CAM_ISP_HW_VFE_IN_LCR &&
		rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)
		val |= (1 << rsrc_data->reg_data->extern_reg_update_shift);

	if (camif_lite_res->res_id == CAM_ISP_HW_VFE_IN_PDLIB)
		val |= (1 << rsrc_data->reg_data->operating_mode_shift);

	cam_io_w_mb(val, rsrc_data->mem_base +
		rsrc_data->common_reg->core_cfg_0);

+2 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ struct cam_vfe_camif_lite_ver3_reg {

struct cam_vfe_camif_lite_ver3_reg_data {
	uint32_t     extern_reg_update_shift;
	uint32_t     operating_mode_shift;
	uint32_t     input_mux_sel_shift;
	uint32_t     reg_update_cmd_data;
	uint32_t     epoch_line_cfg;
	uint32_t     sof_irq_mask;
+2 −1
Original line number Diff line number Diff line
@@ -34,10 +34,11 @@ struct cam_vfe_camif_ver3_pp_clc_reg {

struct cam_vfe_camif_ver3_reg_data {
	uint32_t     pp_extern_reg_update_shift;
	uint32_t     lcr_extern_reg_update_shift;
	uint32_t     dual_pd_extern_reg_update_shift;
	uint32_t     extern_reg_update_mask;
	uint32_t     dual_ife_pix_en_shift;
	uint32_t     operating_mode_shift;
	uint32_t     input_mux_sel_shift;

	uint32_t     pixel_pattern_shift;
	uint32_t     pixel_pattern_mask;