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Commit 505dfe76 authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
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drm/amdgpu: modify sdma start sequence 



should fist halt engine, and then doing the register
programing, and later unhalt engine, and finally run
ring_test.

this help fix reloading driver hang issue of SDMA
ring

original sequence is wrong for it programing engine
after unhalt, which will lead to fault behavior when
doing driver reloading after unloaded.

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d72f7c06

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+7 −2
Original line number Diff line number Diff line
@@ -448,7 +448,12 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev) 
		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);



		ring->ready = true;

	}



	cik_sdma_enable(adev, true);



	for (i = 0; i < adev->sdma.num_instances; i++) {

		ring = &adev->sdma.instance[i].ring;

		r = amdgpu_ring_test_ring(ring);

		if (r) {

			ring->ready = false;
@@ -531,8 +536,8 @@ static int cik_sdma_start(struct amdgpu_device *adev) 
	if (r)

		return r;



	/* unhalt the MEs */

	cik_sdma_enable(adev, true);

	/* halt the engine before programing */

	cik_sdma_enable(adev, false);



	/* start the gfx rings and rlc compute queues */

	r = cik_sdma_gfx_resume(adev);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

+6 −2
Original line number Diff line number Diff line
@@ -491,7 +491,11 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) 
		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);



		ring->ready = true;

	}



	sdma_v2_4_enable(adev, true);

	for (i = 0; i < adev->sdma.num_instances; i++) {

		ring = &adev->sdma.instance[i].ring;

		r = amdgpu_ring_test_ring(ring);

		if (r) {

			ring->ready = false;
@@ -582,8 +586,8 @@ static int sdma_v2_4_start(struct amdgpu_device *adev) 
			return -EINVAL;

	}



	/* unhalt the MEs */

	sdma_v2_4_enable(adev, true);

	/* halt the engine before programing */

	sdma_v2_4_enable(adev, false);



	/* start the gfx rings and rlc compute queues */

	r = sdma_v2_4_gfx_resume(adev);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

+11 −4
Original line number Diff line number Diff line
@@ -713,7 +713,15 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 
		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);



		ring->ready = true;

	}



	/* unhalt the MEs */

	sdma_v3_0_enable(adev, true);

	/* enable sdma ring preemption */

	sdma_v3_0_ctx_switch_enable(adev, true);



	for (i = 0; i < adev->sdma.num_instances; i++) {

		ring = &adev->sdma.instance[i].ring;

		r = amdgpu_ring_test_ring(ring);

		if (r) {

			ring->ready = false;
@@ -806,10 +814,9 @@ static int sdma_v3_0_start(struct amdgpu_device *adev) 
		}

	}



	/* unhalt the MEs */

	sdma_v3_0_enable(adev, true);

	/* enable sdma ring preemption */

	sdma_v3_0_ctx_switch_enable(adev, true);

	/* disble sdma engine before programing it */

	sdma_v3_0_ctx_switch_enable(adev, false);

	sdma_v3_0_enable(adev, false);



	/* start the gfx rings and rlc compute queues */

	r = sdma_v3_0_gfx_resume(adev);