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Commit 504ae402 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/cmdparser: Limit clflush to active cachelines 



We only need to clflush those cachelines that we have validated to be
read by the GPU. Userspace typically fills the batch length in
correctly, the exceptions tend to be explicit tests within igt.

v2: Use ptr_mask_bits() to make Mika happy
v3: cmd is not advanced on MI_BBE, so make sure to include an extra
dword in the clflush.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170310115518.13832-1-chris@chris-wilson.co.uk
parent b8473050

drivers/gpu/drm/i915/i915_cmd_parser.c

+14 −11
Original line number Diff line number Diff line
@@ -1279,11 +1279,17 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, 
	 * space. Parsing should be faster in some cases this way.

	 */

	batch_end = cmd + (batch_len / sizeof(*batch_end));

	while (cmd < batch_end) {

	do {

		u32 length;



		if (*cmd == MI_BATCH_BUFFER_END)

		if (*cmd == MI_BATCH_BUFFER_END) {

			if (needs_clflush_after) {

				void *ptr = ptr_mask_bits(shadow_batch_obj->mm.mapping);

				drm_clflush_virt_range(ptr,

						       (void *)(cmd + 1) - ptr);

			}

			break;

		}



		desc = find_cmd(engine, *cmd, desc, &default_desc);

		if (!desc) {
@@ -1323,17 +1329,14 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, 
		}



		cmd += length;

	}



		if  (cmd >= batch_end) {

			DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");

			ret = -EINVAL;

			break;

		}

	} while (1);



	if (ret == 0 && needs_clflush_after)

		drm_clflush_virt_range(shadow_batch_obj->mm.mapping, batch_len);

	i915_gem_object_unpin_map(shadow_batch_obj);



	return ret;

}