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Commit 502a0c77 authored by Vineet Gupta's avatar Vineet Gupta
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ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth values 



pt_regs->event was set with artificial values to identify the low level
system event (syscall trap / breakpoint trap / exceptions / interrupts)

With r8 saving out of the way, the full word can be used to save real
ECR (Exception Cause Register) which helps idenify the event naturally,
including additional info such as cause code, param.
Only for Interrupts, where ECR is not applicable, do we resort to
synthetic non ECR values.

SAVE_ALL_TRAP/EXCEPTIONS can now be merged as they both use ECR with
different runtime values.

The ptrace helpers now use the sub-fields of ECR to distinguish the
events (e.g. vector 0x25 is trap, param 0 is syscall...)

The following benefits will follow:

(1) This centralizes the location of where ECR is saved and will allow
    the cleanup of task->thread.cause_code ECR placeholder which is set
    in non-uniform way. Then ARC VM code can safely rely on it being
    there for purpose of finer grained VM_EXEC dcache flush (based on
    exec fault: I-TLB Miss)

(2) Further, ECR being passed around from low level handlers as arg can
    be eliminated as it is part of standard reg-file in pt_regs

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 352c1d95

arch/arc/include/asm/arcregs.h

+4 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
#define ECR_V_ITLB_MISS			0x21

#define ECR_V_DTLB_MISS			0x22

#define ECR_V_PROTV			0x23

#define ECR_V_TRAP			0x25



/* Protection Violation Exception Cause Code Values */

#define ECR_C_PROTV_INST_FETCH		0x00
@@ -77,6 +78,9 @@ 
#define ECR_C_BIT_DTLB_LD_MISS		8

#define ECR_C_BIT_DTLB_ST_MISS		9



/* Dummy ECR values for Interrupts */

#define event_IRQ1		0x0031abcd

#define event_IRQ2		0x0032abcd



/* Auxiliary registers */

#define AUX_IDENTITY		4

arch/arc/include/asm/entry.h

+9 −22
Original line number Diff line number Diff line
@@ -309,7 +309,7 @@ 
#endif



	/* Save Pre Intr/Exception User SP on kernel stack */

	st.a    sp, [r9, -16]	; Make room for orig_r0, orig_r8, user_r25

	st.a    sp, [r9, -16]	; Make room for orig_r0, ECR, user_r25



	/* CAUTION:

	 * SP should be set at the very end when we are done with everything
@@ -391,9 +391,10 @@ 
 * Note that syscalls are implemented via TRAP which is also a exception

 * from CPU's point of view

 *-------------------------------------------------------------*/

.macro SAVE_ALL_EXCEPTION   marker

.macro SAVE_ALL_SYS



	st      \marker, [sp, 8]	/* orig_r8 */

	lr	r9, [ecr]

	st      r9, [sp, 8]    /* ECR */

	st      r0, [sp, 4]    /* orig_r0, needed only for sys calls */



	/* Restore r9 used to code the early prologue */
@@ -411,20 +412,6 @@ 
	PUSHAX	erbta

.endm



/*--------------------------------------------------------------

 * Save scratch regs for exceptions

 *-------------------------------------------------------------*/

.macro SAVE_ALL_SYS

	SAVE_ALL_EXCEPTION  orig_r8_IS_EXCPN

.endm



/*--------------------------------------------------------------

 * Save scratch regs for sys calls

 *-------------------------------------------------------------*/

.macro SAVE_ALL_TRAP

	SAVE_ALL_EXCEPTION  orig_r8_IS_SCALL

.endm



/*--------------------------------------------------------------

 * Restore all registers used by system call or Exceptions

 * SP should always be pointing to the next free stack element
@@ -452,7 +439,7 @@ 
	RESTORE_R12_TO_R0



	ld  sp, [sp] /* restore original sp */

	/* orig_r0, orig_r8, user_r25 skipped automatically */

	/* orig_r0, ECR, user_r25 skipped automatically */

.endm
@@ -469,7 +456,7 @@ 
#endif



	/* now we are ready to save the remaining context :) */

	st      orig_r8_IS_IRQ1, [sp, 8]    /* Event Type */

	st      event_IRQ1, [sp, 8]    /* Dummy ECR */

	st      0, [sp, 4]    /* orig_r0 , N/A for IRQ */



	SAVE_R0_TO_R12
@@ -494,7 +481,7 @@ 
	ld  r9, [@int2_saved_reg]



	/* now we are ready to save the remaining context :) */

	st      orig_r8_IS_IRQ2, [sp, 8]    /* Event Type */

	st      event_IRQ2, [sp, 8]    /* Dummy ECR */

	st      0, [sp, 4]    /* orig_r0 , N/A for IRQ */



	SAVE_R0_TO_R12
@@ -535,7 +522,7 @@ 
	RESTORE_R12_TO_R0



	ld  sp, [sp] /* restore original sp */

	/* orig_r0, orig_r8, user_r25 skipped automatically */

	/* orig_r0, ECR, user_r25 skipped automatically */

.endm



.macro RESTORE_ALL_INT2
@@ -554,7 +541,7 @@ 
	RESTORE_R12_TO_R0



	ld  sp, [sp] /* restore original sp */

	/* orig_r0, orig_r8, user_r25 skipped automatically */

	/* orig_r0, ECR, user_r25 skipped automatically */

.endm

arch/arc/include/asm/ptrace.h

+20 −16
Original line number Diff line number Diff line
@@ -44,15 +44,24 @@ struct pt_regs { 
	long sp;	/* user/kernel sp depending on where we came from  */

	long orig_r0;



	/*to distinguish bet excp, syscall, irq */

	/*

	 * To distinguish bet excp, syscall, irq

	 * For traps and exceptions, Exception Cause Register.

	 * 	ECR: <00> <VV> <CC> <PP>

	 * 	Last word used by Linux for extra state mgmt (syscall-restart)

	 * For interrupts, use artificial ECR values to note current prio-level

	 */

	union {

		struct {

#ifdef CONFIG_CPU_BIG_ENDIAN

		/* so that assembly code is same for LE/BE */

		unsigned long orig_r8:16, event:16;

			unsigned long state:8, ecr_vec:8,

				      ecr_cause:8, ecr_param:8;

#else

		unsigned long event:16, orig_r8:16;

			unsigned long ecr_param:8, ecr_cause:8,

				      ecr_vec:8, state:8;

#endif

		long orig_r8_word;

		};

		unsigned long event;

	};



	long user_r25;
@@ -94,11 +103,13 @@ struct callee_regs { 
/* return 1 if PC in delay slot */

#define delay_mode(regs) ((regs->status32 & STATUS_DE_MASK) == STATUS_DE_MASK)



#define in_syscall(regs)    (regs->event & orig_r8_IS_SCALL)

#define in_brkpt_trap(regs) (regs->event & orig_r8_IS_BRKPT)

#define in_syscall(regs)    ((regs->ecr_vec == ECR_V_TRAP) && !regs->ecr_param)

#define in_brkpt_trap(regs) ((regs->ecr_vec == ECR_V_TRAP) && regs->ecr_param)



#define syscall_wont_restart(regs) (regs->event |= orig_r8_IS_SCALL_RESTARTED)

#define syscall_restartable(regs) !(regs->event &  orig_r8_IS_SCALL_RESTARTED)

#define STATE_SCALL_RESTARTED	0x01



#define syscall_wont_restart(reg) (reg->state |= STATE_SCALL_RESTARTED)

#define syscall_restartable(reg) !(reg->state &  STATE_SCALL_RESTARTED)



#define current_pt_regs()					\

({								\
@@ -115,11 +126,4 @@ static inline long regs_return_value(struct pt_regs *regs) 


#endif /* !__ASSEMBLY__ */



#define orig_r8_IS_SCALL		0x0001

#define orig_r8_IS_SCALL_RESTARTED	0x0002

#define orig_r8_IS_BRKPT		0x0004

#define orig_r8_IS_EXCPN		0x0008

#define orig_r8_IS_IRQ1			0x0010

#define orig_r8_IS_IRQ2			0x0020



#endif /* __ASM_PTRACE_H */

arch/arc/kernel/asm-offsets.c

+1 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ int main(void) 
	BLANK();



	DEFINE(PT_status32, offsetof(struct pt_regs, status32));

	DEFINE(PT_orig_r8, offsetof(struct pt_regs, orig_r8_word));

	DEFINE(PT_event, offsetof(struct pt_regs, event));

	DEFINE(PT_sp, offsetof(struct pt_regs, sp));

	DEFINE(PT_r0, offsetof(struct pt_regs, r0));

	DEFINE(PT_r1, offsetof(struct pt_regs, r1));

arch/arc/kernel/entry.S

+12 −9
Original line number Diff line number Diff line
@@ -142,7 +142,7 @@ VECTOR reserved ; Reserved Exceptions 
.endr



#include <linux/linkage.h>   /* ARC_{EXTRY,EXIT} */

#include <asm/entry.h>       /* SAVE_ALL_{INT1,INT2,TRAP...} */

#include <asm/entry.h>       /* SAVE_ALL_{INT1,INT2,SYS...} */

#include <asm/errno.h>

#include <asm/arcregs.h>

#include <asm/irqflags.h>
@@ -495,8 +495,6 @@ tracesys_exit: 
trap_with_param:



	; stop_pc info by gdb needs this info

	stw orig_r8_IS_BRKPT, [sp, PT_orig_r8]



	mov r0, r12

	lr  r1, [efa]

	mov r2, sp
@@ -541,7 +539,7 @@ ARC_ENTRY EV_Trap 
	lr  r9, [erstatus]



	SWITCH_TO_KERNEL_STK

	SAVE_ALL_TRAP

	SAVE_ALL_SYS



	;------- (4) What caused the Trap --------------

	lr     r12, [ecr]
@@ -696,8 +694,17 @@ not_exception: 


#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS



	; Level 2 interrupt return Path - from hardware standpoint

	bbit0  r10, STATUS_A2_BIT, not_level2_interrupt



	;------------------------------------------------------------------

	; However the context returning might not have taken L2 intr itself

	; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret

	; Special considerations needed for the context which took L2 intr



	ld   r9, [sp, PT_event]        ; Ensure this is L2 intr context

	brne r9, event_IRQ2, 149f



	;------------------------------------------------------------------

	; if L2 IRQ interrupted a L1 ISR,  we'd disbaled preemption earlier

	; so that sched doesnt move to new task, causing L1 to be delayed
@@ -705,19 +712,15 @@ not_exception: 
	; things to what they were, before returning from L2 context

	;----------------------------------------------------------------



	ldw  r9, [sp, PT_orig_r8]      ; get orig_r8 to make sure it is

	brne r9, orig_r8_IS_IRQ2, 149f ; infact a L2 ISR ret path



	ld r9, [sp, PT_status32]       ; get statu32_l2 (saved in pt_regs)

	bbit0 r9, STATUS_A1_BIT, 149f  ; L1 not active when L2 IRQ, so normal



	; A1 is set in status32_l2

	; decrement thread_info->preempt_count (re-enable preemption)

	GET_CURR_THR_INFO_FROM_SP   r10

	ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]



	; paranoid check, given A1 was active when A2 happened, preempt count

	; must not be 0 beccause we would have incremented it.

	; must not be 0 because we would have incremented it.

	; If this does happen we simply HALT as it means a BUG !!!

	cmp     r9, 0

	bnz     2f