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Commit 4fcac83b authored by Heiko Stuebner's avatar Heiko Stuebner
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ARM: dts: rockchip: add gpu nodes on rk3066/rk3188 



The old Cortex-A9 socs use Mali400 GPUs with 4 pixel processors.
This adds the core gpu nodes with the per-soc interrupts but sharing
the core node.

Rockchip SoCs use only one clock to supply the GPUs

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 451ef43b

arch/arm/boot/dts/rk3066a.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -610,6 +610,30 @@ 
	};

};



&gpu {

	compatible = "rockchip,rk3066-mali", "arm,mali-400";

	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "gp",

			  "gpmmu",

			  "pp0",

			  "pp0mmu",

			  "pp1",

			  "pp1mmu",

			  "pp2",

			  "pp2mmu",

			  "pp3",

			  "pp3mmu";

};



&i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c0_xfer>;

arch/arm/boot/dts/rk3188.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -553,6 +553,30 @@ 
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;

};



&gpu {

	compatible = "rockchip,rk3188-mali", "arm,mali-400";

	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "gp",

			  "gpmmu",

			  "pp0",

			  "pp0mmu",

			  "pp1",

			  "pp1mmu",

			  "pp2",

			  "pp2mmu",

			  "pp3",

			  "pp3mmu";

};



&i2c0 {

	compatible = "rockchip,rk3188-i2c";

	pinctrl-names = "default";

arch/arm/boot/dts/rk3xxx.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -117,6 +117,17 @@ 
		clock-output-names = "xin24m";

	};



	gpu: gpu@10090000 {

		compatible = "arm,mali-400";

		reg = <0x10090000 0x10000>;

		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;

		clock-names = "core", "bus";

		assigned-clocks = <&cru ACLK_GPU>;

		assigned-clock-rates = <100000000>;

		resets = <&cru SRST_GPU>;

		status = "disabled";

	};



	L2: l2-cache-controller@10138000 {

		compatible = "arm,pl310-cache";

		reg = <0x10138000 0x1000>;