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Commit 4fa04380 authored by James Liao's avatar James Liao
Browse files

clk: mediatek: Add fixed clocks support for Mediatek SoC. 



This patch adds fixed clocks support by using CCF fixed-rate
clock implementation.

Signed-off-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: default avatarDaniel Kurtz <djkurtz@chromium.org>
parent e02940fc

drivers/clk/mediatek/clk-mtk.c

+23 −0
Original line number Diff line number Diff line
@@ -49,6 +49,29 @@ struct clk_onecell_data * __init mtk_alloc_clk_data(unsigned int clk_num) 
	return NULL;

}



void __init mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,

		int num, struct clk_onecell_data *clk_data)

{

	int i;

	struct clk *clk;



	for (i = 0; i < num; i++) {

		const struct mtk_fixed_clk *rc = &clks[i];



		clk = clk_register_fixed_rate(NULL, rc->name, rc->parent,

				rc->parent ? 0 : CLK_IS_ROOT, rc->rate);



		if (IS_ERR(clk)) {

			pr_err("Failed to register clk %s: %ld\n",

					rc->name, PTR_ERR(clk));

			continue;

		}



		if (clk_data)

			clk_data->clks[rc->id] = clk;

	}

}



void __init mtk_clk_register_factors(const struct mtk_fixed_factor *clks,

		int num, struct clk_onecell_data *clk_data)

{

drivers/clk/mediatek/clk-mtk.h

+17 −0
Original line number Diff line number Diff line
@@ -26,6 +26,23 @@ struct clk; 


#define MHZ (1000 * 1000)



struct mtk_fixed_clk {

	int id;

	const char *name;

	const char *parent;

	unsigned long rate;

};



#define FIXED_CLK(_id, _name, _parent, _rate) {		\

		.id = _id,				\

		.name = _name,				\

		.parent = _parent,			\

		.rate = _rate,				\

	}



void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,

		int num, struct clk_onecell_data *clk_data);



struct mtk_fixed_factor {

	int id;

	const char *name;