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Commit 4f98c554 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Nirmal Abraham
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msm: mdss: update the MDSS DSI ULPS exit sequence 



Add change to exit the DSI ULPS mode after enabling the DSI
escape clock and before enabling the DSI PLL. Check for the
DSI PLL unlock error bit and clear it before enabling the
DSI PLL to avoid false error interrupt after turning on
the PLL.

Change-Id: I53042fed9e4e45b64f75190abd4a295c0bc76baa
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent fe0bf0e3

drivers/video/fbdev/msm/msm_mdss_io_8974.c

+31 −2
Original line number Diff line number Diff line
@@ -2568,7 +2568,8 @@ int mdss_dsi_post_clkon_cb(void *priv, 
		if (ctrl->phy_power_off || mmss_clamp)

			mdss_dsi_phy_power_on(ctrl, mmss_clamp);

	}

	if ((clk & MDSS_DSI_LINK_CLK) && (l_type == MDSS_DSI_LINK_HS_CLK)) {



	if ((clk & MDSS_DSI_LINK_CLK) && (l_type == MDSS_DSI_LINK_LP_CLK)) {

		if (ctrl->ulps && mmss_clamp) {

			/*

			 * ULPS Entry Request. This is needed if the lanes were
@@ -2612,8 +2613,12 @@ int mdss_dsi_post_clkon_cb(void *priv, 
		mdss_dsi_split_link_clk_cfg(ctrl, 1);



		/* Enable HS TX driver in DSI PHY if applicable */

		if ((clk & MDSS_DSI_LINK_CLK) &&

				(l_type == MDSS_DSI_LINK_HS_CLK))

			mdss_dsi_phy_hstx_drv_ctrl(ctrl, true);

	}





error:

	return rc;

}
@@ -2727,6 +2732,30 @@ int mdss_dsi_pre_clkon_cb(void *priv, 
		}

	}



	/* Disable dynamic clock gating*/

	if (ctrl->mdss_util->dyn_clk_gating_ctrl)

		ctrl->mdss_util->dyn_clk_gating_ctrl(0);



	if ((clk_type & MDSS_DSI_LINK_CLK) &&

		(l_type == MDSS_DSI_LINK_HS_CLK)) {

		u32 data = 0;



		data = MIPI_INP((ctrl->ctrl_io.base) + 0x0120);

		/*

		 * For 12nm PHY, the PLL unlock bit in DSI_CLK_STATUS gets set

		 * when PLL is turned off. When device comes out of static

		 * screen without the DSI controller getting power collapsed,

		 * the bit might not clear sometimes. Clear the bit before

		 * turning ON the PLL. This avoids false error interrupt due to

		 * PLL unlocked bit after PLL is turned ON.

		 */

		if (data & BIT(16)) {

			pr_debug("pll unlocked: 0x%x\n", data);

			MIPI_OUTP((ctrl->ctrl_io.base) + 0x120, BIT(16));

		}



	}



	if ((clk_type & MDSS_DSI_LINK_CLK) &&

		(new_state == MDSS_DSI_CLK_ON) &&

		!ctrl->panel_data.panel_info.cont_splash_enabled)