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Commit 4f8c483a authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-4.11' of... 

Merge tag 'phy-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into usb-next

Kishon writes:

phy: for 4.11

 *) Add USB HSIC and HS phy driver for Qualcomm's SoC
 *) Add USB3 PHY driver for Broadcom NSP SoC
 *) Make sun4i-usb-phy driver to be used for V3s USB PHY
 *) Misc fixes and cleanups

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parents 4ddecf76 0b10f64d

Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt

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Broadcom USB3 phy binding for northstar plus SoC

The USB3 phy is internal to the SoC and is accessed using mdio interface.



Required mdio bus properties:

- reg: Should be 0x0 for SoC internal USB3 phy

- #address-cells: must be 1

- #size-cells: must be 0



Required USB3 PHY properties:

- compatible: should be "brcm,nsp-usb3-phy"

- reg: USB3 Phy address on SoC internal MDIO bus and it should be 0x10.

- usb3-ctrl-syscon: handler of syscon node defining physical address

  of usb3 control register.

- #phy-cells: must be 0



Required usb3 control properties:

- compatible: should be "brcm,nsp-usb3-ctrl"

- reg: offset and length of the control registers



Example:



	mdio@0 {

		reg = <0x0>;

		#address-cells = <1>;

		#size-cells = <0>;



		usb3_phy: usb-phy@10 {

			compatible = "brcm,nsp-usb3-phy";

			reg = <0x10>;

			usb3-ctrl-syscon = <&usb3_ctrl>;

			#phy-cells = <0>;

			status = "disabled";

		};

	};



	usb3_ctrl: syscon@104408 {

		compatible = "brcm,nsp-usb3-ctrl", "syscon";

		reg = <0x104408 0x3fc>;

	};

Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt

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Qualcomm's USB HS PHY



PROPERTIES



- compatible:

    Usage: required

    Value type: <string>

    Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the

                following:



                        "qcom,usb-hs-phy-apq8064"

                        "qcom,usb-hs-phy-msm8916"

                        "qcom,usb-hs-phy-msm8974"



- #phy-cells:

    Usage: required

    Value type: <u32>

    Definition: Should contain 0



- clocks:

    Usage: required

    Value type: <prop-encoded-array>

    Definition: Should contain clock specifier for the reference and sleep

                clocks



- clock-names:

    Usage: required

    Value type: <stringlist>

    Definition: Should contain "ref" and "sleep" for the reference and sleep

                clocks respectively



- resets:

    Usage: required

    Value type: <prop-encoded-array>

    Definition: Should contain the phy and POR resets



- reset-names:

    Usage: required

    Value type: <stringlist>

    Definition: Should contain "phy" and "por" for the phy and POR resets

                respectively



- v3p3-supply:

    Usage: required

    Value type: <phandle>

    Definition: Should contain a reference to the 3.3V supply



- v1p8-supply:

    Usage: required

    Value type: <phandle>

    Definition: Should contain a reference to the 1.8V supply



- extcon:

    Usage: optional

    Value type: <prop-encoded-array>

    Definition: Should contain the vbus extcon



- qcom,init-seq:

    Usage: optional

    Value type: <u8 array>

    Definition: Should contain a sequence of ULPI address and value pairs to

                program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related

                to Device Mode Eye Diagram test. The addresses are offsets

                from the ULPI_EXT_VENDOR_SPECIFIC address, for example,

                <0x1 0x53> would mean "write the value 0x53 to address 0x81".



EXAMPLE



otg: usb-controller {

	ulpi {

		phy {

			compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy";

			#phy-cells = <0>;

			clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;

			clock-names = "ref", "sleep";

			resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;

			reset-names = "phy", "por";

			v3p3-supply = <&pm8941_l24>;

			v1p8-supply = <&pm8941_l6>;

			extcon = <&smbb>;

			qcom,init-seq = /bits/ 8 <0x1 0x63>;

		};

	};

};

Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt

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Qualcomm's USB HSIC PHY



PROPERTIES



- compatible:

    Usage: required

    Value type: <string>

    Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the

		following:



			"qcom,usb-hsic-phy-mdm9615"

			"qcom,usb-hsic-phy-msm8974"



- #phy-cells:

    Usage: required

    Value type: <u32>

    Definition: Should contain 0



- clocks:

    Usage: required

    Value type: <prop-encoded-array>

    Definition: Should contain clock specifier for phy, calibration and

                a calibration sleep clock



- clock-names:

    Usage: required

    Value type: <stringlist>

    Definition: Should contain "phy, "cal" and "cal_sleep"



- pinctrl-names:

    Usage: required

    Value type: <stringlist>

    Definition: Should contain "init" and "default" in that order



- pinctrl-0:

    Usage: required

    Value type: <prop-encoded-array>

    Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch

                free state



- pinctrl-1:

    Usage: required

    Value type: <prop-encoded-array>

    Definition: List of pinctrl settings to apply to mux out the HSIC pins



EXAMPLE



usb-controller {

	ulpi {

		phy {

			compatible = "qcom,usb-hsic-phy-msm8974",

				     "qcom,usb-hsic-phy";

			#phy-cells = <0>;

			pinctrl-names = "init", "default";

			pinctrl-0 = <&hsic_sleep>;

			pinctrl-1 = <&hsic_default>;

			clocks = <&gcc GCC_USB_HSIC_CLK>,

				 <&gcc GCC_USB_HSIC_IO_CAL_CLK>,

				 <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;

			clock-names = "phy", "cal", "cal_sleep";

			assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>;

			assigned-clock-rates = <960000>;

		};

	};

};

Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt

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@@ -10,6 +10,7 @@ Required properties: 
  * allwinner,sun8i-a23-usb-phy

  * allwinner,sun8i-a33-usb-phy

  * allwinner,sun8i-h3-usb-phy

  * allwinner,sun8i-v3s-usb-phy

  * allwinner,sun50i-a64-usb-phy

- reg : a list of offset + length pairs

- reg-names :

Documentation/devicetree/bindings/ufs/ufs-qcom.txt

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@@ -29,7 +29,6 @@ Optional properties: 
- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply

- vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply

- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply

- vddp-ref-clk-always-on : specifies if this supply needs to be kept always on



Example: