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Commit 4f4e65d2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'omap-fixes-for-linus' of... 

Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6

* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (25 commits)
  OMAP2/3: DMTIMER: Clear pending interrupts when stopping a timer
  PM debug: Fix warning when no CONFIG_DEBUG_FS
  OMAP3: PM: DSS PM_WKEN to refill DMA
  OMAP: timekeeping: time should not stop during suspend
  OMAP3: PM: Force write last pad config register into save area
  OMAP: omap3_pm_get_suspend_state() error ignored in pwrdm_suspend_get()
  OMAP3: PM: Enable wake-up from McBSP2, 3 and 4 modules
  OMAP3: PM debug: fix build error when !CONFIG_DEBUG_FS
  OMAP3: PM: Removing redundant and potentially dangerous PRCM configration
  OMAP3: Fixed ARM aux ctrl register save/restore
  OMAP3: CPUidle: Fixed timer resolution
  OMAP3: PM: Remove duplicate code blocks
  OMAP3: PM: Disable interrupt controller AUTOIDLE before WFI
  OMAP3: PM: Enable system control module autoidle
  OMAP3: PM: Ack pending interrupts before entering suspend
  omap: Enable GPMC clock in gpmc_init
  OMAP1 clock: fix for "BUG: spinlock lockup on CPU#0"
  OMAP4: clocks: Fix the clksel_rate struct DPLL divs
  OMAP4: PRCM: Fix the base address for CHIRONSS reg defines
  OMAP: dma_chan[lch_head].flag & OMAP_DMA_ACTIVE tested twice in omap_dma_unlink_lch()
  ...
parents f6760aa0 5c3db36b

arch/arm/mach-omap1/clock.c

+3 −3
Original line number Diff line number Diff line
@@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) 
	struct mpu_rate * ptr;

	unsigned long dpll1_rate, ref_rate;



	dpll1_rate = clk_get_rate(ck_dpll1_p);

	ref_rate = clk_get_rate(ck_ref_p);

	dpll1_rate = ck_dpll1_p->rate;

	ref_rate = ck_ref_p->rate;



	for (ptr = omap1_rate_table; ptr->rate; ptr++) {

		if (ptr->xtal != ref_rate)
@@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) 
	long highest_rate;

	unsigned long ref_rate;



	ref_rate = clk_get_rate(ck_ref_p);

	ref_rate = ck_ref_p->rate;



	highest_rate = -EINVAL;

arch/arm/mach-omap2/clock34xx_data.c

+0 −4
Original line number Diff line number Diff line
@@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = { 
	.name		= "dpll4_m3x2_ck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &dpll4_m3_ck,

	.init		= &omap2_init_clksel_parent,

	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),

	.enable_bit	= OMAP3430_PWRDN_TV_SHIFT,

	.flags		= INVERT_ENABLE,
@@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = { 
	.name		= "dpll4_m6x2_ck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &dpll4_m6_ck,

	.init		= &omap2_init_clksel_parent,

	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),

	.enable_bit	= OMAP3430_PWRDN_EMU_PERIPH_SHIFT,

	.flags		= INVERT_ENABLE,
@@ -1047,7 +1045,6 @@ static struct clk iva2_ck = { 
	.name		= "iva2_ck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &dpll2_m2_ck,

	.init		= &omap2_init_clksel_parent,

	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),

	.enable_bit	= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,

	.clkdm_name	= "iva2_clkdm",
@@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = { 
	.name		= "gfx_l3_ck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &l3_ick,

	.init		= &omap2_init_clksel_parent,

	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),

	.enable_bit	= OMAP_EN_GFX_SHIFT,

	.recalc		= &followparent_recalc,

arch/arm/mach-omap2/clock44xx_data.c

+31 −31
Original line number Diff line number Diff line
@@ -346,37 +346,37 @@ static struct clk aess_fclk = { 
};



static const struct clksel_rate div31_1to31_rates[] = {

	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },

	{ .div = 2, .val = 1, .flags = RATE_IN_4430 },

	{ .div = 3, .val = 2, .flags = RATE_IN_4430 },

	{ .div = 4, .val = 3, .flags = RATE_IN_4430 },

	{ .div = 5, .val = 4, .flags = RATE_IN_4430 },

	{ .div = 6, .val = 5, .flags = RATE_IN_4430 },

	{ .div = 7, .val = 6, .flags = RATE_IN_4430 },

	{ .div = 8, .val = 7, .flags = RATE_IN_4430 },

	{ .div = 9, .val = 8, .flags = RATE_IN_4430 },

	{ .div = 10, .val = 9, .flags = RATE_IN_4430 },

	{ .div = 11, .val = 10, .flags = RATE_IN_4430 },

	{ .div = 12, .val = 11, .flags = RATE_IN_4430 },

	{ .div = 13, .val = 12, .flags = RATE_IN_4430 },

	{ .div = 14, .val = 13, .flags = RATE_IN_4430 },

	{ .div = 15, .val = 14, .flags = RATE_IN_4430 },

	{ .div = 16, .val = 15, .flags = RATE_IN_4430 },

	{ .div = 17, .val = 16, .flags = RATE_IN_4430 },

	{ .div = 18, .val = 17, .flags = RATE_IN_4430 },

	{ .div = 19, .val = 18, .flags = RATE_IN_4430 },

	{ .div = 20, .val = 19, .flags = RATE_IN_4430 },

	{ .div = 21, .val = 20, .flags = RATE_IN_4430 },

	{ .div = 22, .val = 21, .flags = RATE_IN_4430 },

	{ .div = 23, .val = 22, .flags = RATE_IN_4430 },

	{ .div = 24, .val = 23, .flags = RATE_IN_4430 },

	{ .div = 25, .val = 24, .flags = RATE_IN_4430 },

	{ .div = 26, .val = 25, .flags = RATE_IN_4430 },

	{ .div = 27, .val = 26, .flags = RATE_IN_4430 },

	{ .div = 28, .val = 27, .flags = RATE_IN_4430 },

	{ .div = 29, .val = 28, .flags = RATE_IN_4430 },

	{ .div = 30, .val = 29, .flags = RATE_IN_4430 },

	{ .div = 31, .val = 30, .flags = RATE_IN_4430 },

	{ .div = 1, .val = 1, .flags = RATE_IN_4430 },

	{ .div = 2, .val = 2, .flags = RATE_IN_4430 },

	{ .div = 3, .val = 3, .flags = RATE_IN_4430 },

	{ .div = 4, .val = 4, .flags = RATE_IN_4430 },

	{ .div = 5, .val = 5, .flags = RATE_IN_4430 },

	{ .div = 6, .val = 6, .flags = RATE_IN_4430 },

	{ .div = 7, .val = 7, .flags = RATE_IN_4430 },

	{ .div = 8, .val = 8, .flags = RATE_IN_4430 },

	{ .div = 9, .val = 9, .flags = RATE_IN_4430 },

	{ .div = 10, .val = 10, .flags = RATE_IN_4430 },

	{ .div = 11, .val = 11, .flags = RATE_IN_4430 },

	{ .div = 12, .val = 12, .flags = RATE_IN_4430 },

	{ .div = 13, .val = 13, .flags = RATE_IN_4430 },

	{ .div = 14, .val = 14, .flags = RATE_IN_4430 },

	{ .div = 15, .val = 15, .flags = RATE_IN_4430 },

	{ .div = 16, .val = 16, .flags = RATE_IN_4430 },

	{ .div = 17, .val = 17, .flags = RATE_IN_4430 },

	{ .div = 18, .val = 18, .flags = RATE_IN_4430 },

	{ .div = 19, .val = 19, .flags = RATE_IN_4430 },

	{ .div = 20, .val = 20, .flags = RATE_IN_4430 },

	{ .div = 21, .val = 21, .flags = RATE_IN_4430 },

	{ .div = 22, .val = 22, .flags = RATE_IN_4430 },

	{ .div = 23, .val = 23, .flags = RATE_IN_4430 },

	{ .div = 24, .val = 24, .flags = RATE_IN_4430 },

	{ .div = 25, .val = 25, .flags = RATE_IN_4430 },

	{ .div = 26, .val = 26, .flags = RATE_IN_4430 },

	{ .div = 27, .val = 27, .flags = RATE_IN_4430 },

	{ .div = 28, .val = 28, .flags = RATE_IN_4430 },

	{ .div = 29, .val = 29, .flags = RATE_IN_4430 },

	{ .div = 30, .val = 30, .flags = RATE_IN_4430 },

	{ .div = 31, .val = 31, .flags = RATE_IN_4430 },

	{ .div = 0 },

};

arch/arm/mach-omap2/cpuidle34xx.c

+1 −1
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev, 
	local_irq_enable();

	local_fiq_enable();



	return (u32)timespec_to_ns(&ts_idle)/1000;

	return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;

}



/**

arch/arm/mach-omap2/gpmc.c

+2 −0
Original line number Diff line number Diff line
@@ -534,6 +534,8 @@ void __init gpmc_init(void) 
		BUG();

	}



	clk_enable(gpmc_l3_clk);



	l = gpmc_read_reg(GPMC_REVISION);

	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

	/* Set smart idle mode and automatic L3 clock gating */