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Commit 4f341a5e authored by Fenghua Yu's avatar Fenghua Yu Committed by Thomas Gleixner
Browse files

x86/intel_rdt: Add scheduler hook 



Hook the x86 scheduler code to update closid based on whether the current
task is assigned to a specific closid or running on a CPU assigned to a
specific closid.

Signed-off-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com>
Cc: "Tony Luck" <tony.luck@intel.com>
Cc: "Shaohua Li" <shli@fb.com>
Cc: "Sai Prakhya" <sai.praneeth.prakhya@intel.com>
Cc: "Peter Zijlstra" <peterz@infradead.org>
Cc: "Stephane Eranian" <eranian@google.com>
Cc: "Dave Hansen" <dave.hansen@intel.com>
Cc: "David Carrillo-Cisneros" <davidcc@google.com>
Cc: "Nilay Vaish" <nilayvaish@gmail.com>
Cc: "Vikas Shivappa" <vikas.shivappa@linux.intel.com>
Cc: "Ingo Molnar" <mingo@elte.hu>
Cc: "Borislav Petkov" <bp@suse.de>
Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>
Link: http://lkml.kernel.org/r/1477692289-37412-10-git-send-email-fenghua.yu@intel.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 60ec2440

arch/x86/include/asm/intel_rdt.h

+42 −0
Original line number Diff line number Diff line 
#ifndef _ASM_X86_INTEL_RDT_H

#define _ASM_X86_INTEL_RDT_H



#ifdef CONFIG_INTEL_RDT_A



#include <linux/jump_label.h>



#include <asm/intel_rdt_common.h>



#define IA32_L3_QOS_CFG		0xc81

#define IA32_L3_CBM_BASE	0xc90

#define IA32_L2_CBM_BASE	0xd10
@@ -176,4 +180,42 @@ ssize_t rdtgroup_schemata_write(struct kernfs_open_file *of, 
				char *buf, size_t nbytes, loff_t off);

int rdtgroup_schemata_show(struct kernfs_open_file *of,

			   struct seq_file *s, void *v);



/*

 * intel_rdt_sched_in() - Writes the task's CLOSid to IA32_PQR_MSR

 *

 * Following considerations are made so that this has minimal impact

 * on scheduler hot path:

 * - This will stay as no-op unless we are running on an Intel SKU

 *   which supports resource control and we enable by mounting the

 *   resctrl file system.

 * - Caches the per cpu CLOSid values and does the MSR write only

 *   when a task with a different CLOSid is scheduled in.

 */

static inline void intel_rdt_sched_in(void)

{

	if (static_branch_likely(&rdt_enable_key)) {

		struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);

		int closid;



		/*

		 * If this task has a closid assigned, use it.

		 * Else use the closid assigned to this cpu.

		 */

		closid = current->closid;

		if (closid == 0)

			closid = this_cpu_read(cpu_closid);



		if (closid != state->closid) {

			state->closid = closid;

			wrmsr(MSR_IA32_PQR_ASSOC, state->rmid, closid);

		}

	}

}



#else



static inline void intel_rdt_sched_in(void) {}



#endif /* CONFIG_INTEL_RDT_A */

#endif /* _ASM_X86_INTEL_RDT_H */

arch/x86/kernel/cpu/intel_rdt.c

+0 −1
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ 
#include <linux/cacheinfo.h>

#include <linux/cpuhotplug.h>



#include <asm/intel_rdt_common.h>

#include <asm/intel-family.h>

#include <asm/intel_rdt.h>

arch/x86/kernel/cpu/intel_rdt_rdtgroup.c

+3 −0
Original line number Diff line number Diff line
@@ -292,6 +292,9 @@ static void move_myself(struct callback_head *head) 
		kfree(rdtgrp);

	}



	/* update PQR_ASSOC MSR to make resource group go into effect */

	intel_rdt_sched_in();



	kfree(callback);

}

arch/x86/kernel/process_32.c

+4 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ 
#include <asm/debugreg.h>

#include <asm/switch_to.h>

#include <asm/vm86.h>

#include <asm/intel_rdt.h>



void __show_regs(struct pt_regs *regs, int all)

{
@@ -299,5 +300,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) 


	this_cpu_write(current_task, next_p);



	/* Load the Intel cache allocation PQR MSR. */

	intel_rdt_sched_in();



	return prev_p;

}

arch/x86/kernel/process_64.c

+4 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
#include <asm/switch_to.h>

#include <asm/xen/hypervisor.h>

#include <asm/vdso.h>

#include <asm/intel_rdt.h>



__visible DEFINE_PER_CPU(unsigned long, rsp_scratch);
@@ -473,6 +474,9 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) 
			loadsegment(ss, __KERNEL_DS);

	}



	/* Load the Intel cache allocation PQR MSR. */

	intel_rdt_sched_in();



	return prev_p;

}