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Commit 4f2ebe00 authored by Lucas Stach's avatar Lucas Stach Committed by Bjorn Helgaas
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PCI: designware: Parse bus-range property from devicetree 



This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.

Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found.  We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.

[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarPratyush Anand <pratyush.anand@st.com>
Acked-by: default avatarMohit Kumar <mohit.kumar@st.com>
parent b14a3d17

Documentation/devicetree/bindings/pci/designware-pcie.txt

+3 −0
Original line number Diff line number Diff line
@@ -23,3 +23,6 @@ Required properties: 


Optional properties:

- reset-gpio: gpio pin number of power good signal

- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to

  specify this property, to keep backwards compatibility a range of 0x00-0xff

  is assumed if not present)

drivers/pci/host/pcie-designware.c

+11 −0
Original line number Diff line number Diff line
@@ -500,6 +500,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp) 
		}

	}



	ret = of_pci_parse_bus_range(np, &pp->busn);

	if (ret < 0) {

		pp->busn.name = np->name;

		pp->busn.start = 0;

		pp->busn.end = 0xff;

		pp->busn.flags = IORESOURCE_BUS;

		dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",

			ret, &pp->busn);

	}



	if (!pp->dbi_base) {

		pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,

					resource_size(&pp->cfg));
@@ -794,6 +804,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) 


	sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;

	pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);

	pci_add_resource(&sys->resources, &pp->busn);



	return 1;

}

drivers/pci/host/pcie-designware.h

+1 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ struct pcie_port { 
	struct resource		cfg;

	struct resource		io;

	struct resource		mem;

	struct resource		busn;

	struct pcie_port_info	config;

	int			irq;

	u32			lanes;