ARM64: dts: Prepare configs for Amlogic Meson GXBaby

dts-dirs += altera

dts-dirs += amd

dts-dirs += amlogic

dts-dirs += apm

dts-dirs += arm

dts-dirs += broadcom

always		:= $(dtb-y)

subdir-y	:= $(dts-dirs)

clean-files	:= *.dtb

/*

 * Copyright (c) 2016 Andreas Färber

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual

 * licensing only applies to this file, and not this project as a

 * whole.

 *

 *  a) This library is free software; you can redistribute it and/or

 *     modify it under the terms of the GNU General Public License as

 *     published by the Free Software Foundation; either version 2 of the

 *     License, or (at your option) any later version.

 *

 *     This library is distributed in the hope that it will be useful,

 *     but WITHOUT ANY WARRANTY; without even the implied warranty of

 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *     GNU General Public License for more details.

 *

 * Or, alternatively,

 *

 *  b) Permission is hereby granted, free of charge, to any person

 *     obtaining a copy of this software and associated documentation

 *     files (the "Software"), to deal in the Software without

 *     restriction, including without limitation the rights to use,

 *     copy, modify, merge, publish, distribute, sublicense, and/or

 *     sell copies of the Software, and to permit persons to whom the

 *     Software is furnished to do so, subject to the following

 *     conditions:

 *

 *     The above copyright notice and this permission notice shall be

 *     included in all copies or substantial portions of the Software.

 *

 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES

 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 *     OTHER DEALINGS IN THE SOFTWARE.

 */

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {

	compatible = "amlogic,meson-gxbb";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;

	aliases {

		serial0 = &uart_AO;

		serial1 = &uart_A;

	};

	cpus {

		#address-cells = <0x2>;

		#size-cells = <0x0>;

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

		};

		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

		};

		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x2>;

			enable-method = "psci";

		};

		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x3>;

			enable-method = "psci";

		};

	};

	arm-pmu {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;

	};

	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};

	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,

			     <GIC_PPI 14

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,

			     <GIC_PPI 11

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,

			     <GIC_PPI 10

			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;

	};

	xtal: xtal-clk {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

		clock-output-names = "xtal";

		#clock-cells = <0>;

	};

	soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		cbus: cbus@c1100000 {

			compatible = "simple-bus";

			reg = <0x0 0xc1100000 0x0 0x100000>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;

			uart_A: serial@84c0 {

				compatible = "amlogic,meson-uart";

				reg = <0x0 0x084c0 0x0 0x14>;

				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;

				clocks = <&xtal>;

				status = "disabled";

			};

		};

		gic: interrupt-controller@c4301000 {

			compatible = "arm,gic-400";

			reg = <0x0 0xc4301000 0 0x1000>,

			      <0x0 0xc4302000 0 0x2000>,

			      <0x0 0xc4304000 0 0x2000>,

			      <0x0 0xc4306000 0 0x2000>;

			interrupt-controller;

			interrupts = <GIC_PPI 9

				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

			#interrupt-cells = <3>;

			#address-cells = <0>;

		};

		aobus: aobus@c8100000 {

			compatible = "simple-bus";

			reg = <0x0 0xc8100000 0x0 0x100000>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;

			uart_AO: serial@4c0 {

				compatible = "amlogic,meson-uart";

				reg = <0x0 0x004c0 0x0 0x14>;

				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;

				clocks = <&xtal>;

				status = "disabled";

			};

		};

		apb: apb@d0000000 {

			compatible = "simple-bus";

			reg = <0x0 0xd0000000 0x0 0x200000>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;

		};

	};

};