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Commit 4e659dbe authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Andy Gross
Browse files

firmware: qcom: scm: Expose secure IO service 



The secure IO service provides operations for reading and writing secure
memory from non-secure mode, expose this API through SCM.

Reviewed-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent e691b48d

drivers/firmware/qcom_scm-32.c

+18 −0
Original line number Diff line number Diff line
@@ -596,3 +596,21 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, 
{

	return -ENODEV;

}



int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,

			unsigned int *val)

{

	int ret;



	ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr);

	if (ret >= 0)

		*val = ret;



	return ret < 0 ? ret : 0;

}



int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)

{

	return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,

				     addr, val);

}

drivers/firmware/qcom_scm-64.c

+31 −0
Original line number Diff line number Diff line
@@ -439,3 +439,34 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, 


	return ret;

}



int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,

			unsigned int *val)

{

	struct qcom_scm_desc desc = {0};

	struct arm_smccc_res res;

	int ret;



	desc.args[0] = addr;

	desc.arginfo = QCOM_SCM_ARGS(1);



	ret = qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ,

			    &desc, &res);

	if (ret >= 0)

		*val = res.a1;



	return ret < 0 ? ret : 0;

}



int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)

{

	struct qcom_scm_desc desc = {0};

	struct arm_smccc_res res;



	desc.args[0] = addr;

	desc.args[1] = val;

	desc.arginfo = QCOM_SCM_ARGS(2);



	return qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,

			     &desc, &res);

}

drivers/firmware/qcom_scm.c

+12 −0
Original line number Diff line number Diff line
@@ -333,6 +333,18 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) 
}

EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);



int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)

{

	return __qcom_scm_io_readl(__scm->dev, addr, val);

}

EXPORT_SYMBOL(qcom_scm_io_readl);



int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)

{

	return __qcom_scm_io_writel(__scm->dev, addr, val);

}

EXPORT_SYMBOL(qcom_scm_io_writel);



/**

 * qcom_scm_is_available() - Checks if SCM is available

 */

drivers/firmware/qcom_scm.h

+6 −0
Original line number Diff line number Diff line
@@ -30,6 +30,12 @@ extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); 
#define QCOM_SCM_CMD_CORE_HOTPLUGGED	0x10

extern void __qcom_scm_cpu_power_down(u32 flags);



#define QCOM_SCM_SVC_IO			0x5

#define QCOM_SCM_IO_READ		0x1

#define QCOM_SCM_IO_WRITE		0x2

extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);

extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);



#define QCOM_SCM_SVC_INFO		0x6

#define QCOM_IS_CALL_AVAIL_CMD		0x1

extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,

include/linux/qcom_scm.h

+4 −0
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ extern int qcom_scm_set_remote_state(u32 state, u32 id); 
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);

extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);

extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);

extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);

extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);

#else

static inline

int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
@@ -73,5 +75,7 @@ qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; } 
static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }

static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }

static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }

static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }

static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }

#endif

#endif