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Commit 4e1c1875 authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: Reset MPCC muxes during init 



During HW initialization, instead of assuming or
detecting the existing MPCC mux configuration and
then removing existing planes, reset all the MPCC
muxes.

Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9a0beb39

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+4 −9
Original line number Diff line number Diff line
@@ -702,7 +702,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 


static void dcn10_init_hw(struct dc *dc)

{

	int i, opp_id;

	int i;

	struct abm *abm = dc->res_pool->abm;

	struct dmcu *dmcu = dc->res_pool->dmcu;

	struct dce_hwseq *hws = dc->hwseq;
@@ -765,13 +765,8 @@ static void dcn10_init_hw(struct dc *dc) 
		}

	}



	/* Initialize MPC tree based on HW values */

	for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {

		struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];

		struct mpc_tree *mpc_tree_params = &(opp->mpc_tree_params);



		dc->res_pool->mpc->funcs->init_mpcc_list_from_hw(dc->res_pool->mpc, mpc_tree_params);

	}

	/* Reset all MPCC muxes */

	dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct timing_generator *tg = dc->res_pool->timing_generators[i];
@@ -783,7 +778,7 @@ static void dcn10_init_hw(struct dc *dc) 


		pipe_ctx->plane_res.hubp = hubp;

		hubp->mpcc_id = i;

		hubp->opp_id = dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);

		hubp->opp_id = 0xf;

		hubp->power_gated = false;



		if (hubp->opp_id != 0xf)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c

+28 −30
Original line number Diff line number Diff line
@@ -101,16 +101,6 @@ void mpc1_assert_idle_mpcc(struct mpc *mpc, int id) 
			1, 100000);

}



static int mpc1_get_opp_id(struct mpc *mpc, int mpcc_id)

{

	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

	unsigned int opp_id = 0xF;



	REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);



	return opp_id;

}



struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)

{

	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
@@ -333,24 +323,44 @@ void mpc1_remove_mpcc( 
	}

}



static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)

{

	mpcc->mpcc_id = mpcc_inst;

	mpcc->dpp_id = 0xf;

	mpcc->mpcc_bot = NULL;

	mpcc->blnd_cfg.overlap_only = false;

	mpcc->blnd_cfg.global_alpha = 0xff;

	mpcc->blnd_cfg.global_gain = 0xff;

	mpcc->sm_cfg.enable = false;

}



/*

 * Reset the MPCC HW status by disconnecting all muxes.

 *

 * Parameters:

 * [in/out] mpc		- MPC context.

 * [in]     mpcc_id	- The MPCC physical instance to reset.

 *

 * Return:  void

 */

void mpc1_reset_mpcc(

	struct mpc *mpc,

	int mpcc_id)

void mpc1_mpc_init(struct mpc *mpc)

{

	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);

	int mpcc_id;

	int opp_id;



	mpc10->mpcc_in_use_mask = 0;

	for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {

		REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);

		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);



		mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);

	}



	for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {

		if (REG(MUX[opp_id]))

			REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, 0xf);

	}

}



void mpc1_init_mpcc_list_from_hw(
@@ -399,27 +409,15 @@ void mpc1_init_mpcc_list_from_hw( 
	}

}



static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)

{

	mpcc->mpcc_id = mpcc_inst;

	mpcc->dpp_id = 0xf;

	mpcc->mpcc_bot = NULL;

	mpcc->blnd_cfg.overlap_only = false;

	mpcc->blnd_cfg.global_alpha = 0xff;

	mpcc->blnd_cfg.global_gain = 0xff;

	mpcc->sm_cfg.enable = false;

}



const struct mpc_funcs dcn10_mpc_funcs = {

	.insert_plane = mpc1_insert_plane,

	.remove_mpcc = mpc1_remove_mpcc,

	.reset_mpcc = mpc1_reset_mpcc,

	.mpc_init = mpc1_mpc_init,

	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,

	.wait_for_idle = mpc1_assert_idle_mpcc,

	.assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,

	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,

	.update_blending = mpc1_update_blending,

	.get_opp_id = mpc1_get_opp_id,

};



void dcn10_mpc_construct(struct dcn10_mpc *mpc10,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h

+2 −4
Original line number Diff line number Diff line
@@ -146,10 +146,8 @@ void mpc1_remove_mpcc( 
	struct mpc_tree *tree,

	struct mpcc *mpcc);



void mpc1_reset_mpcc(

	struct mpc *mpc,

	int mpcc_id);



void mpc1_mpc_init(

	struct mpc *mpc);



void mpc1_assert_idle_mpcc(

	struct mpc *mpc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

+1 −6
Original line number Diff line number Diff line
@@ -151,13 +151,10 @@ struct mpc_funcs { 
	 *

	 * Parameters:

	 * [in/out] mpc		- MPC context.

	 * [in]     mpcc_id	- The MPCC physical instance to reset.

	 *

	 * Return:  void

	 */

	void (*reset_mpcc)(

		struct mpc *mpc,

		int mpcc_id);

	void (*mpc_init)(struct mpc *mpc);



	/*

	 * Update the blending configuration for a specified MPCC.
@@ -186,8 +183,6 @@ struct mpc_funcs { 
		struct mpc *mpc,

		struct mpc_tree *tree);



	int (*get_opp_id)(struct mpc *mpc, int mpcc_id);



};



#endif