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Commit 4e02bea8 authored by Nikhil Badola's avatar Nikhil Badola Committed by Greg Kroah-Hartman
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drivers: usb: fsl: Define usb control register mask for w1c bits 



Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit

Signed-off-by: default avatarNikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f4fdfaa2

drivers/usb/host/ehci-fsl.c

+16 −9
Original line number Diff line number Diff line
@@ -127,14 +127,16 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev) 


	/* Enable USB controller, 83xx or 8536 */

	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)

		setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);

		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,

				CONTROL_REGISTER_W1C_MASK, 0x4);



	/*

	 * Enable UTMI phy and program PTS field in UTMI mode before asserting

	 * controller reset for USB Controller version 2.5

	 */

	if (pdata->has_fsl_erratum_a007792) {

		writel_be(CTRL_UTMI_PHY_EN, hcd->regs + FSL_SOC_USB_CTRL);

		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,

				CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);

		writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);

	}
@@ -200,8 +202,10 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 
	case FSL_USB2_PHY_ULPI:

		if (pdata->have_sysif_regs && pdata->controller_ver) {

			/* controller version 1.6 or above */

			clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);

			setbits32(non_ehci + FSL_SOC_USB_CTRL,

			clrbits32(non_ehci + FSL_SOC_USB_CTRL,

				  CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);

			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,

					CONTROL_REGISTER_W1C_MASK,

					ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);

		}

		portsc |= PORT_PTS_ULPI;
@@ -216,13 +220,15 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 
	case FSL_USB2_PHY_UTMI_DUAL:

		if (pdata->have_sysif_regs && pdata->controller_ver) {

			/* controller version 1.6 or above */

			setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);

			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,

					CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);

			mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to

						become stable - 10ms*/

		}

		/* enable UTMI PHY */

		if (pdata->have_sysif_regs)

			setbits32(non_ehci + FSL_SOC_USB_CTRL,

			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,

					CONTROL_REGISTER_W1C_MASK,

					CTRL_UTMI_PHY_EN);

		portsc |= PORT_PTS_UTMI;

		break;
@@ -245,7 +251,8 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 
	ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);



	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)

		setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);

		clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,

				CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);



	return 0;

}

drivers/usb/host/ehci-fsl.h

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
#define SNOOP_SIZE_2GB		0x1e



/* control Register Bit Masks */

#define CONTROL_REGISTER_W1C_MASK       0x00020000  /* W1C: PHY_CLK_VALID */

#define ULPI_INT_EN             (1<<0)

#define WU_INT_EN               (1<<1)

#define USB_CTRL_USB_EN         (1<<2)