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Commit 4db8e6d2 authored by Stefan Kristiansson's avatar Stefan Kristiansson Committed by Jason Cooper
Browse files

irqchip: or1k-pic: Migrate from arch/openrisc/ 



In addition to consolidating the or1k-pic with other interrupt
controllers, this makes OpenRISC less tied to its on-cpu
interrupt controller.

All or1k-pic specific parts are moved out of irq.c and into
drivers/irqchip/irq-or1k-pic.c

In that transition, the functionality have been divided into
three chip variants.
One that handles level triggered interrupts, one that handles edge
triggered interrupts and one that handles the interrupt
controller that is present in the or1200 OpenRISC cpu
implementation.

Signed-off-by: default avatarStefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Link: https://lkml.kernel.org/r/1401136302-27654-1-git-send-email-stefan.kristiansson@saunalahti.fi


Acked-by: default avatarJonas Bonn <jonas@southpole.se>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 1b0a76c1

Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt

0 → 100644
+23 −0
Original line number Diff line number Diff line 
OpenRISC 1000 Programmable Interrupt Controller



Required properties:



- compatible : should be "opencores,or1k-pic-level" for variants with

  level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with

  edge triggered interrupt lines or "opencores,or1200-pic" for machines

  with the non-spec compliant or1200 type implementation.



  "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",

  but this is only for backwards compatibility.



- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.



Example:



intc: interrupt-controller {

	compatible = "opencores,or1k-pic-level";

	interrupt-controller;

	#interrupt-cells = <1>;

};

arch/openrisc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ config OPENRISC 
	select GENERIC_STRNLEN_USER

	select MODULES_USE_ELF_RELA

	select HAVE_DEBUG_STACKOVERFLOW

	select OR1K_PIC



config MMU

	def_bool y

arch/openrisc/include/asm/irq.h

+3 −0
Original line number Diff line number Diff line
@@ -24,4 +24,7 @@ 


#define NO_IRQ		(-1)



void handle_IRQ(unsigned int, struct pt_regs *);

extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));



#endif /* __ASM_OPENRISC_IRQ_H__ */

arch/openrisc/kernel/irq.c

+13 −133
Original line number Diff line number Diff line
@@ -16,11 +16,10 @@ 


#include <linux/interrupt.h>

#include <linux/init.h>

#include <linux/of.h>

#include <linux/ftrace.h>

#include <linux/irq.h>

#include <linux/irqchip.h>

#include <linux/export.h>

#include <linux/irqdomain.h>

#include <linux/irqflags.h>



/* read interrupt enabled status */
@@ -37,150 +36,31 @@ void arch_local_irq_restore(unsigned long flags) 
}

EXPORT_SYMBOL(arch_local_irq_restore);





/* OR1K PIC implementation */



/* We're a couple of cycles faster than the generic implementations with

 * these 'fast' versions.

 */



static void or1k_pic_mask(struct irq_data *data)

{

	mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));

}



static void or1k_pic_unmask(struct irq_data *data)

{

	mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));

}



static void or1k_pic_ack(struct irq_data *data)

{

	/* EDGE-triggered interrupts need to be ack'ed in order to clear

	 * the latch.

	 * LEVEL-triggered interrupts do not need to be ack'ed; however,

	 * ack'ing the interrupt has no ill-effect and is quicker than

	 * trying to figure out what type it is...

	 */



	/* The OpenRISC 1000 spec says to write a 1 to the bit to ack the

	 * interrupt, but the OR1200 does this backwards and requires a 0

	 * to be written...

	 */



#ifdef CONFIG_OR1K_1200

	/* There are two oddities with the OR1200 PIC implementation:

	 * i)  LEVEL-triggered interrupts are latched and need to be cleared

	 * ii) the interrupt latch is cleared by writing a 0 to the bit,

	 *     as opposed to a 1 as mandated by the spec

	 */



	mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));

#else

	WARN(1, "Interrupt handling possibly broken\n");

	mtspr(SPR_PICSR, (1UL << data->hwirq));

#endif

}



static void or1k_pic_mask_ack(struct irq_data *data)

{

	/* Comments for pic_ack apply here, too */



#ifdef CONFIG_OR1K_1200

	mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));

	mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));

#else

	WARN(1, "Interrupt handling possibly broken\n");

	mtspr(SPR_PICMR, (1UL << data->hwirq));

	mtspr(SPR_PICSR, (1UL << data->hwirq));

#endif

}



#if 0

static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type)

{

	/* There's nothing to do in the PIC configuration when changing

	 * flow type.  Level and edge-triggered interrupts are both

	 * supported, but it's PIC-implementation specific which type

	 * is handled. */



	return irq_setup_alt_chip(data, flow_type);

}

#endif



static struct irq_chip or1k_dev = {

	.name = "or1k-PIC",

	.irq_unmask = or1k_pic_unmask,

	.irq_mask = or1k_pic_mask,

	.irq_ack = or1k_pic_ack,

	.irq_mask_ack = or1k_pic_mask_ack,

};



static struct irq_domain *root_domain;



static inline int pic_get_irq(int first)

void __init init_IRQ(void)

{

	int hwirq;



	hwirq = ffs(mfspr(SPR_PICSR) >> first);

	if (!hwirq)

		return NO_IRQ;

	else

		hwirq = hwirq + first -1;



	return irq_find_mapping(root_domain, hwirq);

	irqchip_init();

}



static void (*handle_arch_irq)(struct pt_regs *);



static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)

void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))

{

	irq_set_chip_and_handler_name(irq, &or1k_dev,

				      handle_level_irq, "level");

	irq_set_status_flags(irq, IRQ_LEVEL | IRQ_NOPROBE);



	return 0;

	handle_arch_irq = handle_irq;

}



static const struct irq_domain_ops or1k_irq_domain_ops = {

	.xlate = irq_domain_xlate_onecell,

	.map = or1k_map,

};



/*

 * This sets up the IRQ domain for the PIC built in to the OpenRISC

 * 1000 CPU.  This is the "root" domain as these are the interrupts

 * that directly trigger an exception in the CPU.

 */

static void __init or1k_irq_init(void)

void handle_IRQ(unsigned int irq, struct pt_regs *regs)

{

	struct device_node *intc = NULL;



	/* The interrupt controller device node is mandatory */

	intc = of_find_compatible_node(NULL, NULL, "opencores,or1k-pic");

	BUG_ON(!intc);



	/* Disable all interrupts until explicitly requested */

	mtspr(SPR_PICMR, (0UL));



	root_domain = irq_domain_add_linear(intc, 32,

					    &or1k_irq_domain_ops, NULL);

}



void __init init_IRQ(void)

{

	or1k_irq_init();

}



void __irq_entry do_IRQ(struct pt_regs *regs)

{

	int irq = -1;

	struct pt_regs *old_regs = set_irq_regs(regs);



	irq_enter();



	while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)

	generic_handle_irq(irq);



	irq_exit();

	set_irq_regs(old_regs);

}



void __irq_entry do_IRQ(struct pt_regs *regs)

{

	handle_arch_irq(regs);

}

drivers/irqchip/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -53,6 +53,10 @@ config CLPS711X_IRQCHIP 
	select SPARSE_IRQ

	default y



config OR1K_PIC

	bool

	select IRQ_DOMAIN



config ORION_IRQCHIP

	bool

	select IRQ_DOMAIN